參數(shù)資料
型號: 935230900112
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 3/68頁
文件大?。?/td> 234K
代理商: 935230900112
2000 Jan 04
11
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Acceptance code
AC.7 to 0
AC
Acceptance Code
X
Acceptance mask
AM.7 to 0
AM
Acceptance Mask
X
Bus timing 0
BTR0.7
SJW.1
Synchronization Jump Width 1
X
BTR0.6
SJW.0
Synchronization Jump Width 0
X
BTR0.5
BRP.5
Baud Rate Prescaler 5
X
BTR0.4
BRP.4
Baud Rate Prescaler 4
X
BTR0.3
BRP.3
Baud Rate Prescaler 3
X
BTR0.2
BRP.2
Baud Rate Prescaler 2
X
BTR0.1
BRP.1
Baud Rate Prescaler 1
X
BTR0.0
BRP.0
Baud Rate Prescaler 0
X
Bus timing 1
BTR1.7
SAM
Sampling
X
BTR1.6
TSEG2.2
Time Segment 2.2
X
BTR1.5
TSEG2.1
Time Segment 2.1
X
BTR1.4
TSEG2.0
Time Segment 2.0
X
BTR1.3
TSEG1.3
Time Segment 1.3
X
BTR1.2
TSEG1.2
Time Segment 1.2
X
BTR1.1
TSEG1.1
Time Segment 1.1
X
BTR1.0
TSEG1.0
Time Segment 1.0
X
Output control
OC.7
OCTP1
Output Control Transistor P1
X
OC.6
OCTN1
Output Control Transistor N1
X
OC.5
OCPOL1
Output Control Polarity 1
X
OC.4
OCTP0
Output Control Transistor P0
X
OC.3
OCTN0
Output Control Transistor N0
X
OC.2
OCPOL0
Output Control Polarity 0
X
OC.1
OCMODE1
Output Control Mode 1
X
OC.0
OCMODE0
Output Control Mode 0
X
Transmit buffer
TXB
Transmit Buffer
X
Receive buffer
RXB
Receive Buffer
X; note 5
Clock divider
CDR
Clock Divider Register
00000000
(Intel);
00000101
(Motorola)
X
REGISTER
BIT
SYMBOL
NAME
VALUE
RESET BY
HARDWARE
SETTING
BIT CR.0 BY
SOFTWARE OR
DUE TO
BUS-OFF
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