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參數(shù)資料
| 型號： | 935235160112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, MO-118, SOT-370-1, SSOP-48 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 100K |
| 代理商： | 935235160112 |
2002 Oct 02
2
Philips Semiconductors
Product specication
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range from 1.2 to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out
architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16373A only)
High-impedance when VCC =0V.
DESCRIPTION
The 74LVC(H)16373A is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One Latch Enable
(LE) input and one Output Enable (OE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices. In 3-state operation, outputs can handle 5 V.
These features allow the use of these devices in a mixed
3.3 and 5 V environment.
The 74LVC(H)16373A consists of 2 sections of eight
D-type transparent latches with 3-state true outputs. When
LE is HIGH, data at the Dn inputs enter the latches. In this
condition the latches are transparent, i.e., a latch output
will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The 74LVCH16373A bus hold data inputs eliminates the
need for external pull up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns
Note
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacity in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay:
CL = 50 pF; VCC = 3.3 V
Dn to Qn
3.0
ns
LE to Qn
3.4
ns
CI
input capacitance
5.0
pF
CPD
power dissipation per latch
VCC = 3.3 V; note 1
26
pF
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