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參數(shù)資料
| 型號： | 935238500112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, MO-118AA, SOT-370-1, SSOP3-48 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 168K |
| 代理商： | 935238500112 |
Philips Semiconductors
Product specification
74LVC16374A/
74LVCH16374A
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
1998 Mar 17
7
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V
VM
1/fMAX
tw
tPHL
tPLH
CP INPUT
Qn OUTPUT
SW00078
GND
VOH
VOL
VI
Waveform 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency
tPLZ
tPZL
VI
OE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
tPHZ
VM
tPZH
VX
VY
SW00072
VM
Waveform 2. 3-State enable and disable times
VM
SW00079
VI
GND
VM
Dn
INPUT
VI
GND
VM
VOH
Qn
OUTPUT
VOL
CP
INPUT
tsu
th
tsu
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
Waveform 3. Data set-up and hold times for the Dn input to the
CP input
TEST CIRCUIT
PULSE
GENERATOR
RT
VIN
D.U.T.
VOUT
CL
VCC
RL=500
SWITCH POSITION
TEST
SWITCH
tPLH/tPHL
Open
tPLZ/tPZL
2
<VCC
tPHZ/tPZH
GND
Test Circuit for 3-State Outputs
Open
GND
S1
2
<VCC
DEFINITIONS
VCC
t 2.7V
2.7 – 3.6V
VIN
VCC
2.7V
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT
of pulse generators.
SW00047
RL=500
Waveform 4. Load circuitry for switching times
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