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| 型號(hào)： | 935242210557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁(yè)數(shù)： | 97/147頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | 935242210557 |
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1998 Apr 09
53
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 45 Event Counter set 2 Register (EC2R)
Table 46 Event Counter set 1 Source Select Register 1 (EC1SSR)
Table 47 Event Counter set 2 Source Select Register (EC2SSR)
Table 48 Status Bit Addresses (SBA)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
11C
EC5 [9:0]
31 to 22
R
Event Counter Five: this is the fourth 10-bit counter
EC4 [9:0]
21 to 12
R
Event Counter Four: this is the third 10-bit counter
EC3 [11:0]
11 to 0
R
Event Counter Three: this is the second 12-bit counter
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
E4
31 to 24
reserved
ECS2 [5:0] 23 to 18
RW
Event Counter 2 Source: this 6 bit value addresses one of the status bits
ECEN2
17
RW
Event Counter 2 Enable: if this bit is set, event counter 2 is enabled
ECCLR2
16
RW
Event Counter 2 Clear: writing a logic 1 to this bit will clear event counter 2
ECS1 [5:0] 15 to 10
RW
Event Counter 1 Source: this 6 bit value addresses one of the status bits
ECEN1
9
RW
Event Counter 1 Enable: if this bit is set event counter 1 is enabled
ECCLR1
8
RW
Event Counter 1 Clear: writing a logic 1 to this bit will clear event counter 1
ECS0 [5:0]
7 to 2
RW
Event Counter 0 Source: this 6 bit value addresses one of the status bits
ECEN0
1
RW
Event Counter 0 Enable: if this bit is set event counter 0 is enabled
ECCLR0
0
RW
Event Counter 0 Clear: writing a logic 1 to this bit will clear event counter 0
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
E8
31 to 24
reserved
ECS5 [5:0] 23 to 18
RW
Event Counter 5 Source: this 6 bit value addresses one of the status bits
ECEN5
17
RW
Event Counter 5 Enable: if this bit is set the event counter 5 is enabled
ECCLR5
16
RW
Event Counter 5 Clear: writing a logic 1 to this bit will clear event counter 5
ECS4 [5:0] 15 to 10
RW
Event Counter 4 Source: this 6 bit value addresses one of the status bits
ECEN4
9
RW
Event Counter 4 Enable: if this bit is set event counter 4 is enabled
ECCLR4
8
RW
Event Counter 4 Clear: writing a logic 1 to this bit will clear event counter 4
ECS3 [5:0]
7 to 2
RW
Event Counter 3 Source: this 6 bit value addresses one of the status bits
ECEN3
1
RW
Event Counter 3 Enable: if this bit is set event counter 3 is enabled
ECCLR3
0
RW
Event Counter 3 Clear: writing a logic 1 to this bit will clear event counter 3
ADDRESS
(HEX)
STATUS BIT
EVENTS TO BE COUNTED
00
PPEF
number of PCI Parity errors
01
PABO
number of PCI Access errors
02
PPED
every PCI clock cycle with ‘data’ parity error
03
RPS_I1
number of RPS interrupts Task 1
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