2003 Feb 24
2
Philips Semiconductors
Product specication
Hex inverter
74LVC04A
FEATURES
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74LVC04A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC04A provides six inverting buffers.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay nA to nY
CL = 50 pF; VCC = 3.3 V
2.1
ns
CI
input capacitance
4.0
pF
CPD
power dissipation capacitance per gate
VCC = 3.3 V; notes 1 and 2
15
pF
TYPE NUMBER
PACKAGE
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC04AD
40 to +125 °C
14
SO14
plastic
SOT108-1
74LVC04ADB
40 to +125 °C
14
SSOP14
plastic
SOT337-1
74LVC04APW
40 to +125 °C
14
TSSOP14
plastic
SOT402-1
74LVC04ABQ
40 to +125 °C
14
DHVQFN14
plastic
SOT762-1