參數(shù)資料
型號(hào)： 935248790551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 34/36頁(yè)
文件大?。?/td> 314K
代理商： 935248790551
Philips Semiconductors
Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31
7
AC CHARACTERISTICS1, 2, 4
VCC = 5V ± 10%, TA = –40_C to 85_C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
Min
Typ3
Max
UNIT
Reset Timing (See Figure 3)
tRES
RESET pulse width
200
ns
Bus Timing5 (See Figure 4)
tAS
A0-A3 setup time to RDN, WRN Low
10
ns
tAH
A0-A3 hold time from RDN, WRN Low
25
ns
tCS
CEN setup time to RDN, WRN Low
0
ns
tCH
CEN hold time from RDN, WRN High
0
ns
tRW
WRN, RDN pulse width
70
ns
tDD
Data valid after RDN Low
55
ns
tDF
Data bus floating after RDN High
25
ns
tDS
Data setup time before WRN or CEN High
25
ns
tDH
Data hold time after WRN or CEN High
0
ns
tRWD
High time between reads and/or writes5, 6
30
ns
Port Timing5 (See Figure 5)
tPS
Port input setup time before RDN Low
0
ns
tPH
Port input hold time after RDN High
0
ns
tPD
OPn output valid from WRN High
100
ns
Interrupt Timing (See Figure 6)
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RxFIFO (RxRDY/FFULL interrupt)
100
ns
Write TxFIFO (TxRDY interrupt)
100
ns
tIR
Reset command (break change interrupt)
100
ns
Stop C/T command (counter interrupt)
100
ns
Read IPCR (input port change interrupt)
100
ns
Write IMR (clear of interrupt mask bit)
100
ns
Clock Timing (See Figure 7)
tCLK
X1/CLK High or Low time
50
ns
fCLK
X1/CLK frequency
0.1
3.6864
8
MHz
tCTC
CTCLK (IP2) High or Low time
55
ns
fCTC
CTCLK (IP2) frequency
0
8
MHz
tRX
RxC High or Low time (16X)
30
ns
fRX
RxC frequency (16X)
(1X)8
0
16
1
MHz
tTX
TxC High or Low time (16X)
30
ns
fTX
TxC frequency
(16X)
(1X)8
0
16
1
MHz
Transmitter Timing (See Figure 8)
tTXD
TxD output delay from TxC external clock input on IP pin
60
ns
tTCS
Output delay from TxC low at OP pin to TxD data output
5
30
ns
Receiver Timing (See Figure 9)
tRXS
RxD data setup time before RxC high at external clock input on IP pin
50
ns
tRXH
RxD data hold time after RxC high at external clock input on IP pin
50
ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25
°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7K to VCC.
5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
7. Minimum frequencies are not tested but are guaranteed by design. Crystal frequencies 2 to 4 MHz.
8. Clocks for 1X mode should be symmetrical.
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