參數(shù)資料
型號(hào)： 935257890551
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL ENCODER, PQCC84
封裝： PLASTIC, SOT-189-2, LCC-84
文件頁(yè)數(shù)： 22/42頁(yè)
文件大?。?/td> 289K
代理商： 935257890551
1996 Jul 08
29
Philips Semiconductors
Preliminary specication
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
CHARACTERISTICS
VDDD = 4.75 to 5.25 V; Tamb = 0 to +70 °C; unless otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply
VDDD
digital supply voltage
4.75
5.25
V
VDDA
analog supply voltage
4.75
5.25
V
IDDD
digital supply current
note 1
250
mA
IDDA
analog supply current
note 1
110
mA
Inputs
VIL
LOW level input voltage
(except SDA, SCL, AP, SP and XTALI)
0.5
+0.8
V
VIH
HIGH level input voltage
(except LLC, SDA, SCL, AP, SP and XTALI)
2.0
VDDD + 0.5 V
HIGH level input voltage (LLC)
2.4
VDDD + 0.5 V
ILI
input leakage current
1
A
CI
input capacitance
clocks
10
pF
data
8pF
I/Os at high impedance
8pF
Outputs
VOL
LOW level output voltage
(except SDA and XTALO)
note 2
0
0.6
V
VOH
HIGH level output voltage
(except LLC, SDA, and XTALO)
note 2
2.4
VDDD + 0.5 V
HIGH level output voltage (LLC)
note 2
2.6
VDDD + 0.5 V
I2C-bus; SDA and SCL
VIL
LOW level input voltage
0.5
+1.5
V
VIH
HIGH level input voltage
3.0
VDDD + 0.5 V
II
input current
VI = LOW or HIGH
10
+10
A
VOL
LOW level output voltage (SDA)
IOL =3mA
0.4
V
IO
output current
during acknowledge
3
mA
Clock timing (LLC)
TLLC
cycle time
note 3
34
41
ns
δ
duty factor tHIGH/TLLC
note 4
40
60
%
tr
rise time
note 3
5ns
tf
fall time
note 3
6ns
Input timing
tSU
input data set-up time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
6
ns
tHD
input data hold time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
3
ns
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