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參數(shù)資料
| 型號： | 935260531512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 4/67頁 |
| 文件大?。?/td> | 400K |
| 代理商： | 935260531512 |
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1998
Apr
07
12
Philips
Semiconductors
Product
specication
8-bit
Flash
microcontrollers
P89C738;
P89C739
P2.0/A8 to
P2.2/A10
54 to 56
44 to 46
38 to 34
24 to 31
21 to 28
Port 2: P2.0 to P2.7; 8-bit quasi-bidirectional I/O Port with internal
pull-ups. Port 2 can sink/source one TTL (= 4 LSTTL) input. It can
drive CMOS inputs without external pull-ups.
Port 2 alternative functions are: A8 to A15; during access to
external memories (RAM/ROM) that use 16-bit addresses (MOVX
@DPTR) Port 2 emits the high-order address byte (A8 to A15).
P2.3/A11 to
P2.4/A12
58 to 59
48 to 49
P2.5/A13 to
P2.7/A15
61, 64
and 65
51, 54
and 55
23 to 25
PSEN
67
56
26
32
29
Program Store Enable output: read strobe to the external program
memory via Port 0 and Port 2. It is activated twice each machine
cycle during fetches from external program memory.
When executing out of external program memory two activations of
PSEN are skipped during each access to external data memory.
PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs. It
can drive CMOS inputs without external pull-ups.
ALE/WE(2)
68
57
27
33
30
Address Latch Enable output: latches the lower byte of the
address during access to external memory in normal operation. It is
activated every six oscillator periods except during an external data
memory access. ALE can sink/source 8 LSTTL inputs. It can drive
CMOS inputs without an external pull-up.
WE: Write Enable.
EA/VPP
2
59293531
External Access input: when during reset, EA is held at a TTL
HIGH level, the CPU executes from the internal program ROM.
When EA is held at a TTL LOW level during reset, the CPU executes
out of external program memory via Port 0 and Port 2. EA is not
allowed to oat. EA is latched during reset and don’t care after reset.
VPP: programming supply voltage.
P0.7/AD7 to
P0.4/AD4
3, 5, 6
and 9
60, 61, 62
and 1
30 to 33
36 to 43
32 to 39
Port 0: P0.7 to P0.0; 8-bit open-drain bidirectional I/O port. It is also
the multiplexed low-order address and data bus during accesses to
external memory: AD0 to AD7. During these accesses internal
pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.
P0.3/AD3 to
P0.2/AD2
11 to 12
3 to 4
22 to 21
P0.1/AD1 to
P0.0/AD0
14 to 15
6 to 7
20 to 19
VDD
17
9
18
44
40
Power supply (+5 V) pin for normal operation, Idle mode and
Power-down mode.
SYMBOL
PIN(1)
DESCRIPTION
PLCC68
QFP64
PLCC44
QFP44
DIP40
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