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參數(shù)資料
| 型號： | 935261032118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO24 |
| 封裝： | PLASTIC, SOT-340, SSOP-24 |
| 文件頁數(shù)： | 3/34頁 |
| 文件大小： | 293K |
| 代理商： | 935261032118 |
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1999 Jan 22
11
Philips Semiconductors
Product specication
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver
UAA3220TS
Notes
1. 100% AM modulation (ASK); available power from generator into a 50
load.
2. With external matching network, to transform the impedance to 50
.
3.
f = 10 kHz; available power from generator into a 50 load.
4. Measured at the RF input connector of the test board into a 50
load; fi(RF) = 25 MHz to 1 GHz.
5. The data frequency range can be varied by changing C30 to C32 (see Figs 9 and 10) to match other bit rates.
Data frequency determined by data slicer application.
6. ton = 50 ms; toff = 138 ms; P = Psens + 3 dB.
7. The given turn-on time is only valid during strobing by pin PWD; if the IC is strobed on and off by the supply voltage
the turn-on time will be longer.
8. LC tank circuit (L60, C60) tuned to maximum phase slope.
9. GPMA is typically 6 dB lower when measured in the application, because of the load of the ceramic filter.
Limiter
Ri(LIN)
limiter input resistance
40
48
56
k
Buffer
RCPC
data buffer output resistance at pin 17
24
30
36
k
Gbuffer
data buffer AC gain
12
13
14
dB
RCPA,CPB
data buffer output resistance at
pins 15 and 16
120
150
180
k
Data slicer; see Chapter “DC characteristics”
Bds
internal data slicer bandwidth
50
100
kHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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