參數資料
型號： 935261128557
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, SOT-407, QFP-100
文件頁數： 28/47頁
文件大?。?/td> 192K
代理商： 935261128557
1999 Sep 27
34
Philips Semiconductors
Preliminary specication
Digital PC-camera signal processor
SAA8113HL
VOL(rms)
nominal output level at high level
(RMS value)
0.34
V
Vo2(p-p)
nominal output level at low level
(peak-to-peak value)
23.5
mV
Vo2(rms)
nominal output level at low level
(RMS value)
8.3
mV
Vo(max)(p-p)
maximum output level (peak-to-peak value)
2
V
S/N
signal-to-noise ratio
40
dB
THD
total harmonic distortion at high level
60
50
dB
Zi
input impedance
5
k
Zo
output impedance
100
B-3 dB
frequency range (
3 dB)
0.1
20
kHz
BIASSING
Iref
reference current
25
A
Data input/output timing; (see Fig.13)
DATA INPUTS RELATED TO XIN (CCD9 TO CCD0 AND KNOB4)
tsu(i)(D)
data input setup time
note 2
9.5
ns
th(i)(D)
data input hold time
note 2
10.5
ns
DATA OUTPUTS RELATED TO XIN (OUTBVEN, OUTGAIN, SMP, LED, SDATA, SCLK, STROBE AND STNDBY)
th(o)(D)
data output delay time
note 2
57
ns
td(o)(D)
data output hold time
note 2
3
5.5
ns
PPG high speed pulse timing; CL = 10 pF (see Fig.14)
td1
FH2 fall time delay w.r.t. the rising edge of
FH1
3
0
+3
ns
td2
FH2 rise time delay w.r.t. the falling edge of
FH1
3
0
+3
ns
td3
FR fall time delay w.r.t. the rising edge of
FH1
01
2
ns
td3_delayed
FR_delayed fall time delay w.r.t. the rising
edge of FH1
7
8
10
ns
td4_wide
FCDS fall time delay w.r.t. the rising edge of
FR_wide
12
3
ns
td4_narrow
FCDS fall time delay w.r.t. the rising edge of
FR_narrow
14
15
16
ns
td5
FH1 fall time delay w.r.t. the rising edge of
FCDS
01
2
ns
td6_wide
FH1 rise time delay w.r.t. the rising edge of
FS_wide
01
2
ns
td6_narrow
FH1 rise time delay w.r.t. the rising edge of
FS_narrow
14
15
16
ns
td7
CLK1 fall time delay w.r.t. the rising edge of
FH1
01
2
ns
SYMBOL
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNIT
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