參數(shù)資料
型號(hào)： 935261504518
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： PLASTIC, SOT-307, QFP-44
文件頁數(shù)： 53/87頁
文件大?。?/td> 440K
代理商： 935261504518
1999 Jul 01
57
Philips Semiconductors
Product specication
9-bit video input processor
SAA7113H
15.2.10 SUBADDRESS 09H
Table 36 Luminance control SA 09, D7 to D0
Note
1. Not to be used with bypassed chrominance trap.
FUNCTION
APER/BPSS BIT
LOGIC LEVEL
DATA BIT
Aperture factor (APER); see Figs 12 to 17
Aperture factor = 0
APER1
0
D1
APER0
0
D0
Aperture factor = 0.25
APER1
0
D1
APER0
1
D0
Aperture factor = 0.5
APER1
1
D1
APER0
0
D0
Aperture factor = 1.0
APER1
1
D1
APER0
1
D0
Update time interval for analog AGC value (UPTCV)
Horizontal update (once per line)
UPTCV
0
D2
Vertical update (once per eld)
UPTCV
1
D2
Vertical blanking luminance bypass (VBLB)
Active luminance processing
VBLB
0
D3
Chrominance trap and peaking stage are disabled
during VBI lines determined by VREF = 0; see Table 45
VBLB
1
D3
Aperture band-pass (centre frequency) (BPSS)
Centre frequency = 4.1 MHz
BPSS1
0
D5
BPSS0
0
D4
Centre frequency = 3.8 MHz; note 1
BPSS1
0
D5
BPSS0
1
D4
Centre frequency = 2.6 MHz; note 1
BPSS1
1
D5
BPSS0
0
D4
Centre frequency = 2.9 MHz; note 1
BPSS1
1
D5
BPSS0
1
D4
Prelter active (PREF); see Figs 12 to 17
Bypassed
PREF
0
D6
Active
PREF
1
D6
Chrominance trap bypass (BYPS)
Chrominance trap active; default for CVBS mode
BYPS
0
D7
Chrominance trap bypassed; default for S-video mode
BYPS
1
D7
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