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參數(shù)資料
| 型號(hào)： | 935261537112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | DELTA-SIGMA ADC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 152K |
| 代理商： | 935261537112 |
2000 Feb 08
4
Philips Semiconductors
Preliminary specication
Low-voltage low-power stereo audio ADC
UDA1360TS
PINNING
SYMBOL
PIN
DESCRIPTION
VINL
1
left channel input
Vref
2
reference voltage
VINR
3
right channel input
Vref(n)
4
ADC negative reference voltage
Vref(p)
5
ADC positive reference voltage
SFOR
6
data format selection input
PWON
7
power control input
SYSCLK
8
system clock input 256 or 384fs
VDDD
9
digital supply voltage
VSSD
10
digital ground
BCK
11
bit clock input
WS
12
word selection input
DATAO
13
data output
FSEL
14
system clock frequency select
VSSA
15
analog ground
VDDA
16
analog supply voltage
Fig.2 Pin configuration.
handbook, halfpage
UDA1360TS
MGM968
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VINL
Vref
VINR
Vref(n)
Vref(p)
SFOR
PWON
SYSCLK
VDDD
VSSD
BCK
WS
DATAO
FSEL
VSSA
VDDA
FUNCTIONAL DESCRIPTION
System clock
The UDA1360TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable via the static FSEL pin, and the system clock
must be locked in frequency to the digital interface input
signals.
The options are 256fs (FSEL = LOW) and 384fs
(FSEL = HIGH). The sampling frequency range is
5 to 55 kHz.
The BCK clock can be up to 128fs, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: fBCK ≤ 128 × fWS.
Notes:
1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface.
2. For MSB justified formats it is important to have a WS
signal with 50% duty factor.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1360TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
Input level
The overall system gain is proportional to VDDA. The 0 dB
input level is defined as that which gives a
1 dB FS digital
output (relative to the full-scale swing). In addition, an input
gain switch is incorporated with the above definitions.
The UDA1360TS front-end is equipped with a selectable
0 or 6 dB gain, in order to supports 2 V (RMS) input using
a series resistor of 12 k
.
For the definition of the pin settings for 1 or 2 V (RMS)
mode given in Table 1, it is assumed that this resistor is
present as a default component.
If the 2 V (RMS) signal input is not needed, the external
resistor should not be used.
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