參數(shù)資料
型號(hào)： 935261615118
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： 7.50 MM, PLASTIC, SO-28
文件頁(yè)數(shù)： 25/48頁(yè)
文件大小： 356K
代理商： 935261615118
1998 Oct 06
31
Philips Semiconductors
Preliminary specication
Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)
UDA1321
AC CHARACTERISTICS
VDD = 3.3 V; VSS =0V; Tamb =25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Driver characteristics D+ and D
(full-speed mode)
tr
rise time
CL =50pF
4
20
ns
tf
fall time
CL =50pF
4
20
ns
trf(m)
matching rise/fall time (tr/tf)90
110
%
Vcr
output signal crossover voltage
1.3
2.0
V
R(o)driver
driver output resistance
steady-state drive
28
43
Data source timings D+ and D
(full-speed mode)
fi(sample)
audio sample input frequency
5
55
kHz
ffs(D)
full-speed data rate
11.97
12.00
12.03
Mbits/s
tfr
frame interval
0.9995
1.0000
1.0005
ms
tJ1(dif)
source differential jitter to next
transition
3.5
0.0
+3.5
ns
tJ2(dif)
source differential jitter for paired
transitions
4.0
0.0
+4.0
ns
tW(EOP)
source End Of Packet (EOP) width
160
175
ns
tEOP(dif)
differential to EOP transition skew
2.0
+5.0
ns
tJR1
receiver data jitter tolerance to next
transition
18.5
0.0
+18.5
ns
tJR2
receiver data jitter tolerance for
paired transitions
9.0
0.0
+9.0
ns
tEOPR1
EOP width at receiver must reject as
EOP
40
ns
tEOPR2
EOP width at receiver must accept
as EOP
82
ns
Serial input/output data timing; see Fig.9
fclk(sys)
system clock frequency
12
MHz
fi(WS)
word select input frequency
5
55
kHz
tr
rise time
20
ns
tf
fall time
20
ns
tBCK(H)
bit clock HIGH time
55
ns
tBCK(L)
bit clock LOW time
55
ns
ts;DAT
data set-up time
10
ns
th;DAT
data hold time
20
ns
ts;WS
word select set-up time
20
ns
th;WS
word select hold time
10
ns
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