參數(shù)資料
型號： 935261770518
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 1-CH 9-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝： PLASTIC, SOT-341-1, SSOP-28
文件頁數(shù)： 27/27頁
文件大?。?/td> 218K
代理商： 935261770518
1998 Nov 03
9
Philips Semiconductors
Product specication
9-bit analog-to-digital converter
for digital video
TDA8761A
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 511:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb =25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at Tamb =25 °C.
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
a) The current flowing into the resistor ladder is
and the full-scale input range at the converter,
to cover code 0 to code 511, is
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
will be kept reasonably constant from device to device. Consequently variation of the output
codes at a given input voltage depends mainly on the difference VRT VRB and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
4. fi = 10 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz.
5.
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.
Timing (fclk = 30 MHz; CL = 15 pF); see Fig.4; note 11
tds
sampling delay time
3
ns
th
output hold time
4
ns
td
output delay time
VCCO = 4.75 V
10
13
ns
VCCO = 3.15 V
12
15
ns
CL
digital output load
15
pF
3-state output delay times; see Fig.5
tdZH
enable HIGH
5.5
8.5
ns
tdZL
enable LOW
12
15
ns
tdHZ
disable HIGH
19
24
ns
tdLZ
disable LOW
12
15
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
L
V
RT
V
RB
–
R
OB
R
L
R
OT
++
------------------------------------------
=
V
I
R
L
I
L
×
R
L
R
OB
R
L
R
OT
++
------------------------------------------
==
V
RT
(
×
V
RB )
–
0.
˙ 852
V
(
RT
V
RB )
–
×
=
R
L
R
OB
R
L
R
OT
++
------------------------------------------
GER
V
511
V
0
–
() V
i(p-p)
–
V
i(p-p)
----------------------------------------------------
100
×
=
相關PDF資料
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