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參數(shù)資料
| 型號： | 935262318518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 6/43頁 |
| 文件大?。?/td> | 193K |
| 代理商： | 935262318518 |
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1999 May 31
14
Philips Semiconductors
Product specication
Digital video encoder
SAA7126H; SAA7127H
Table 11 Subaddresses 38H and 39H
Table 12 Subaddress 3AH
Table 13 Subaddress 54H
DATA BYTE
DESCRIPTION
GY0 to GY4
gain luminance of RGB (Cr, Y and Cb) output, ranging from (1
1632)to(1+ 1532).
Suggested nominal value =
6 (11010b), depending on external application.
GCD0 to GCD4
gain colour difference of RGB (Cr, Y and Cb) output, ranging from (1
16
32)to(1+
15
32).
Suggested nominal value =
6 (11010b), depending on external application.
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
MP2C1
0
input data is twos complement from MP1 input port (encoder path)
1
input data is straight binary from MP1 input port; default after reset
MP2C2
0
input data is twos complement from MP2 input port (RGB path)
1
input data is straight binary from MP2 input port; default after reset
CSYNC
0
If VBSEN0 = 0, CVBS output signal is switched to CVBS DAC.
If VBSEN0 = 1, luminance output signal is switched to CVBS DAC; default after reset.
1
advanced composite sync is switched to CVBS DAC
DEMOFF
0
Y, Cb and Cr for RGB dematrix is active; default after reset
1
Y, Cb and Cr for RGB dematrix is bypassed
SYMP
0
horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset
1
horizontal and vertical trigger is decoded out of
“CCIR 656” compatible data at MP port
CBENB
0
data from input ports is encoded; default after reset
1
colour bar with xed colours is encoded
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
EDGE1
0
MP1 data is sampled on the rising clock edge; default after reset
1
MP1 data is sampled on the falling clock edge
EDGE2
0
MP2 data is sampled on the rising clock edge; default after reset
1
MP2 data is sampled on the falling clock edge
CCIRS
0
If SYMP = 1, horizontal and vertical trigger is decoded out of
“CCIR 656” compatible data at
MP2 port; default after reset.
1
If SYMP = 1, horizontal and vertical trigger is decoded out of
“CCIR 656” compatible data at
MP1 port.
VPSEN
0
video programming system data insertion is disabled; default after reset
1
video programming system data insertion in line 16 is enabled
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