1999 May 31
17
Philips Semiconductors
Product specication
Digital video encoder
SAA7126H; SAA7127H
Table 21 Logic levels and function of CCRS
Table 22 Subaddress 61H
Table 23 Subaddress 62AH
CCRS1
CCRS0
DESCRIPTION
0
no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5
0
1
cross-colour reduction #1 active; for overall transfer characteristic see Fig.5
1
0
cross-colour reduction #2 active; for overall transfer characteristic see Fig.5
1
cross-colour reduction #3 active; for overall transfer characteristic see Fig.5
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
FISE
0
864 total pixel clocks per line; default after reset
1
858 total pixel clocks per line
PAL
0
NTSC encoding (non-alternating V component)
1
PAL encoding (alternating V component); default after reset
SCBW
0
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4)
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4); default after reset
YGS
0
luminance gain for white
black 100 IRE; default after reset
1
luminance gain for white
black 92.5 IRE including 7.5 IRE set-up of black
INPI
0
PAL switch phase is nominal; default after reset
1
PAL switch phase is inverted compared to nominal if RTC is enabled (see Table 23)
DOWNA
0
DAC for CVBS in normal operational mode; default after reset
1
DAC for CVBS forced to lowest output voltage
DOWNB
0
DACs for R, G and B in normal operational mode
1
DACs for R, G and B forced to lowest output voltage; default after reset
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
RTCE
0
no real-time control of generated subcarrier frequency; default after reset
1
real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for
timing see Fig.13