參數(shù)資料
型號(hào): 935262318557
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL ENCODER, PQFP44
封裝: PLASTIC, QFP-44
文件頁(yè)數(shù): 25/43頁(yè)
文件大?。?/td> 193K
代理商: 935262318557
1999 May 31
31
Philips Semiconductors
Product specication
Digital video encoder
SAA7126H; SAA7127H
Explanation of RTCI data bits
1. The HPLL increment is not evaluated by SAA7126H; SAA7127H.
2. The SAA7126H; SAA7127H generates the subcarrier frequency from the FSCPLL increment if enabled (see item 7.).
3. The PAL bit indicates the line with inverted (R
Y) component of colour difference signal.
4. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line
whenever the reset bit of RTCI input is set to logic 1.
5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7126H; SAA7127H takes this bit instead of the FISE bit
in subaddress 61H.
6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7126H; SAA7127H ignores it’s internally generated
odd/even flag and takes the odd/even bit from RTCI input.
7. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0),
the subcarrier frequency is generated by the SAA7126H; SAA7127H. In the other case (colour detection bit = 1) the
subcarrier frequency is evaluated out of FSCPLL increment.
If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL
increment, independent of the colour detection bit of RTCI input.
Fig.13 RTCI timing.
(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.
(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.
(3) Sequence bit: PAL: 0 = (R
Y) line normal, 1 = (R Y) line inverted; NTSC: 0 = no change.
(4) Reset bit: only from SAA7111 and SAA7112 decoder.
(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(6) Odd/even bit: odd_even from external.
(7) Colour detection: 0 = no colour detected, 1 = colour detected.
(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.
handbook, full pagewidth
128
13
14
19
67
64
69 72 74
68
01
0
22
RTCI
HPLL
increment (1)
FSCPLL increment (2)
H/L transition
count start
4 bits
reserved
valid
sample
invalid
sample
not used in SAA7126H/27H
3 bits
reserved
8/LLC
MHB503
LOW
time slot:
(3)
(4)
(6)
(7)
(8)
(5)
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