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參數資料
| 型號： | 935262321518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 11/43頁 |
| 文件大?。?/td> | 193K |
| 代理商： | 935262321518 |
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1999 May 31
19
Philips Semiconductors
Product specication
Digital video encoder
SAA7126H; SAA7127H
Table 27 Subaddress 6BH
Table 28 Logic levels and function of SRCV1
Table 29 Subaddresses 6CH and 6DH
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
PRCV2
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;
default after reset
1
polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively
ORCV2
0
pin RCV2 is switched to input; default after reset
1
pin RCV2 is switched to output
CBLF
0
If ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is
dened by RCV2S and RCV2E, also during vertical blanking interval); default after reset.
If ORCV2 = LOW and bit SYMP = LOW, the signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset.
1
If ORCV2 = HIGH, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a
reference pulse that is dened by RCV2S and RCV2E, excluding vertical blanking interval,
which is dened by FAL and LAL. If ORCV2 = LOW and bit SYMP = LOW, the signal input
to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking
signal.
PRCV1
0
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after
reset
1
polarity of RCV1 as output is active LOW, falling edge is taken when input
ORCV1
0
pin RCV1 is switched to input; default after reset
1
pin RCV1 is switched to output
TRCV2
0
horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded
frame sync of
“CCIR 656” input (at bit SYMP = HIGH); default after reset
1
horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
SRCV1
denes signal type on pin RCV1; see Table 28
DATA BYTE
AS OUTPUT
AS INPUT
FUNCTION
SRCV11
SRCV10
0
VS
vertical sync each eld; default after reset
0
1
FS
frame sync (odd/even)
1
0
FSEQ
eld sequence, vertical sync every fourth eld (PAL = 0)
or eighth eld (PAL = 1)
1
not applicable
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG
decreases delays of all internally generated timing signals; reference mark: analog output
horizontal sync (leading slope) coincides with active edge of RCV used for triggering at
HTRIG = 39H
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