參數(shù)資料
型號: 935262546118
廠商: NXP SEMICONDUCTORS
元件分類: 總線收發(fā)器
英文描述: ALVC/VCX/A SERIES, 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: PLASTIC, TSSOP2-56
文件頁數(shù): 5/15頁
文件大小: 399K
代理商: 935262546118
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Product Information
74ALVCH16601;
18-bit universal bus
transceiver (3-State)
Information as of 2001-11-09
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Blockdiagram
Parametrics
Description
The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA)latch enable (LEAB and LEBA )
, and clock (CPAB and CPBA) inputs. For A-to-B data flowthe device operates in the transparent mode when LEAB is High.
When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is
stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is
High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA /CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBALEBA and CPBA.
To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Philips Semiconductors; 74ALVCH16601; 18-bit universal bus transceiver (3-State)
file:///G|/imaging/BITTING/mail_pdf/cpl_rework/74alvch16601dgg.html (1 of 3) [1/9/2002 11:47:18 AM]
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