- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄36334 > 935262922551 (NXP SEMICONDUCTORS) SPECIALTY CONSUMER CIRCUIT, PQFP160 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935262922551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁(yè)數(shù)： | 10/147頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | 935262922551 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)
1998 Apr 09
107
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.15.4.3
Transfer conguration
When using ‘dumb’ targets (unable to handshake) or ‘slow’
targets (unable to pull DTACK_RDY immediately), the
cycle length is adjusted by using a programmable cycle
timer. At TIMEOUT in Motorola mode the transfer control
gets into a defined state by finishing the cycle when a slave
is hanging or not able to handshake. In Intel mode the
transfer control waits for RDY = 1 after TIMEOUT, i.e. the
timer reflects the RDY reaction time of the target. In any
TIMEOUT case the Timer overflow Interrupt (TI) flag is set.
The timer starts at the falling edge of
UDS_WRN/LDS_RDN. For initiating a transfer the target
address must be specified (16-bit, pointing to the first byte
to transfer), the transfer direction (WRITE_n) and the
BLOCKLENGTH that indicates how many bytes have to
be transferred. For block transfer a 32-bit DMA start
address (PCI) has to be specified in the DEBI_AD register.
When the BLOCKLENGTH is 1 to 4 bytes the data is
immediately transferred to/from the DEBI_AD register.
Immediate transfer crossing a Dword boundary is not
allowed. Such illegal transfer trials are reported by the
Format Error bit (FE) in the status register. Immediate
transfer starts with the least significant byte/word of the
DEBI_AD register.
The following figures illustrate the protocol of the DEBI bus
for Intel mode transfers. These figures contain no formal
timing specification (see Table 93 for timing) but rather are
intended to help in understanding the operation of the
DEBI interface. The DEBI bus protocol operates in step
with the PCI clock, so it is shown for reference at the
bottom of these diagrams. At slower PCI clock rates, the
DEBI transaction time is proportionally increased. It is not
necessary to connect a PCI clock to the DEBI target
system, since DEBI does not expect target read data or
target driven handshake signals to be synchronous to PCI
clock.
Figure 35 shows the non-incremental mode access in the
fastest possible configuration (TIMEOUT = 0; FAST = 1).
The overhead for this type of access is 2 PCI clock cycles
for address phase plus 2 PCI clock cycles for each data
phase. In this mode, the blocks are easily identified by the
falling edge of ALE indicating a new target address can be
latched.
Larger TIMEOUT values would lead to wider read/write
pulses (pulse width = TIMEOUT + 1 [PCI clock cycles]).
Disabling the FAST mode would force 2 PCI clock cycles
Idle time between read/write strobes. It is not possible to
adjust the address phase timing. It is also assumed in this
figure that the RDY signal is not used (tied to HIGH level).
Use of the RDY signal is allowed in this mode and further
explained in the next example.
Figure 36 shows the incremental mode access. This mode
will produce an address phase prior to each data phase,
and as such has much lower bandwidth than the
non-incremental mode. In the example shown, the RDY
signal is also used, although that is not a requirement of
this mode. The overhead for this type of access is 2 PCI
cycles for address phase plus 2 PCI cycles for data
transfer phase plus 3 PCI cycles for write (4 PCI cycles for
read) Idle time between the data phase and the next
address phase. In the example shown, since RDY was
used with a TIMEOUT of 2, the resulting data phase was
4 PCI cycles, rather than the minimum of 2. In this
example the RDY de-asserts within the same PCI clock
cycle as RDN/WRN, which means RDY LOW is strobed by
the DEBI interface 1 PCI clock cycle after setting
RDN/WRN to LOW (parameter tmin = 1 PCI clock cycle).
Due to this a TIMEOUT = tmin + 1 = 2 (or greater) is
required for flexible access stretching, i.e. synchronizing
the RDY and stretching the access until RDY is released
to HIGH (see description of tmin in the timing parameters;
Table 93). In difference to the example without RDY
usage, increasing the value in TIMEOUT will NOT result in
wider read/write strobes, as long as the TIMEOUT value
does not exceed the RDY LOW phase by more than 1 PCI
clock cycle. Enabling or disabling the FAST mode has no
effect in incremental mode.
It should be noted that the minimum timing illustrated by
these diagrams is not the sustainable data rate by the
SAA7146A through the DEBI interface. PCI-bus latencies,
FIFO fullness, target behaviour and other factors will affect
the sustained data rate. For illustration purposes Table 94
provides indication of peak data rates in various DEBI
configurations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935262922557 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935242220551 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935242220557 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935260698551 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935260698557 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。