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參數(shù)資料
| 型號(hào)： | 935262922551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁(yè)數(shù)： | 103/147頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | 935262922551 |
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1998 Apr 09
59
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 51 Video timing reference codes
Notes
1. F = logic 0 during field 1 and logic 1 during field 2.
2. V = logic 0 elsewhere and logic 1 during field blanking.
3. H = logic 0 in SAV and logic 1 in EAV.
4. P0,P1,P2 and P3: protection bits (see Table 52).
Bits P0,P1,P2 and P3, have states dependent on the states of the bits F, V and H as shown in Table 52. At the receiver
(SAA7146A) this arrangement permits one-bit errors to be corrected. If two-bit errors or up to four-bit errors occur, i. e.
depending on uncoded protection bits, the circuit processes direct on the coded values. In this case the protection bits
are ignored.
SAV and EAV are only decoded and removed from the signal stream (substituted with neighbouring first or last active
video sample), if chosen this way. However, ‘single’ qualified codes of ‘00’ and/or ‘FF’ in the data stream, remain in the
data stream and are processed as data.
BYTE
BIT NUMBER
7 (MSB)
6
5
4
3
2
1
0 (LSB)
First
1
Second
0
Third
0
Fourth
1
F(1)
V(2)
H(3)
P3(4)
P2(4)
P1(4)
P0(4)
Fig.11 Timing of PXQ_x for CCIR 656 at the D1_x port.
handbook, full pagewidth
D1_x (7 to 0)
FFH
MHB052
PXQ_x
D1_x (7 to 0)
LLC
00H
SAV
Cb
Y
Cr
00H
Y
FFH
00H
EAV
Cr
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