參數(shù)資料
型號(hào)： 935263156557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 63/76頁(yè)
文件大?。?/td> 567K
代理商： 935263156557
Philips Semiconductors
Product specification
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
1999 Mar 02
66
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
Standard-mode
I2C-bus
Fast-mode
I2C-bus
UNIT
MIN
MAX
MIN
MAX
I2C Interface timing (refer to Figure 63)
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
Bus free time between a STOP and START condition
4.7
–
1.3
–
s
tHD; STA
Hold time (repeated) START condition. After this period, the
first clock pulse is generated
4.0
–
0.6
–
s
tLOW
LOW period of the SCL clock
4.7
–
1.3
–
s
tHIGH
High period of the SCL clock
4.0
–
0.6
–
s
tSU; STA
Set-up time for a repeated START condition
4.7
–
0.6
–
s
tHD; DAT
Data hold time:
for CBUS competible masters (see Section 9, Notes 1, 3)
for I2C-bus devices
5.0
0 1
–
01
–
0.92
s
tSU; DAT
Data set-up time
250
–
1003
–
ns
tFD, tFC
Rise time of both SDA and SCL signals
–
1000
20 +
0.1Cb4
300
ns
tFD, tFC
Fall time of both SDA and SCL signals
–
300
20 +
0.1Cb4
300
ns
tSU; STO
Set-up time for STOP condition
4.0
–
0.6
–
s
Cb
Capacitive load for each bus line
–
400
–
400
pF
tSP
Pulse width of spikes which must be suppressed by the input
filter
–
0
50
ns
All values referred to VIH and VIL max levels.
NOTES:
1.
A device must internally provide a hold time of at least 300 ns from the SDA signal (referred to the VIH min of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
2.
The maximum tHD,DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
3.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU,DAT > 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line tRmax + tSU,DAT = 1000 + 250 = 1250 ns (according to the standard-mode
I2C-bus specification) before the SCL line is released.
4.
Cb = total capacitance of one bus line in pF.
Table 46.
External clock drive XTAL1 (refer to Figure 57)
SYMBOL
PARAMETER
VARIABLE CLOCK
fCLK = 3.5 to 16 MHz
UNIT
MIN
MAX
tCLK
XTAL1 Period
63
286
ns
tCLKH
XTAL1 HIGH time
20
–
ns
tCLKL
XTAL1 LOW time
20
–
ns
tCLKR
XTAL1 rise time
–
20
ns
tCLKF
XTAL1 fall time
–
20
ns
tCYC 1)
Controller cycle time
0.75
3.4
s
NOTE:
1.
tCYC = 12 fCLK
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