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| 型號： | 935263704557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 接收器 |
| 英文描述： | AM/FM, AUDIO DEMODULATOR, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 16/71頁 |
| 文件大小： | 304K |
| 代理商： | 935263704557 |
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2000 Aug 04
23
Philips Semiconductors
Product specication
Digital TV sound demodulator/decoder
TDA9874A
7.3.3
GENERAL CONFIGURATION REGISTER (GCONR)
The default setting after Power-on reset is 1100 0000.
Table 15 General conguration register (subaddress 1)
Table 16 Description of the general conguration register bits
76543210
P2OUT
P1OUT
STDBY
INIT
CLRPFR
AGCSLOW
AGCOFF
SIFSEL
BIT
SYMBOL
DESCRIPTION
7
P2OUT
General purpose I/O pins 1 and 2: these bits control the general purpose input/output
pins. The contents of these bits is written directly to the corresponding pins. If an input is
desired, the bits must be set to 1 to allow the pins to be pulled to LOW levels externally.
Input from the pins is reected in the device status register (see Section 7.4.1).
Bit P1OUT is recommended to be used for switching an SIF trap for the adjacent picture
carrier in designs that employ such a trap.
6
P1OUT
5
STDBY
Standby mode on/off: if bit STDBY = 1 the TDA9874A is set to the standby mode. Most
functions are disabled and power dissipation is somewhat reduced. If bit STDBY = 0 the
TDA9874A is in its normal mode of operation. On return from standby mode, the device
is in its Power-on reset mode and needs to be re-initialized with data dened by the
user.
4
INIT
Initialize to default settings: if bit INIT = 1 it causes initialization of the TDA9874A to its
default settings. This has the same effect as a Power-on reset. In the event of a conict
between the default settings and any bit set to logic 1 in this register, the bits actually
written to this register will overwrite the default settings. This bit is automatically reset
to 0 after initialization has been completed. When set to logic 0, the TDA9874A is in its
normal mode of operation.
3
CLRPFR
Clear power failure register: if bit CLRPFR = 1 it resets the clear power failure register.
This bit is automatically reset to logic 0 after bit PFR in the device status register has
been read.
2
AGCSLOW
AGC decay time: if bit AGCSLOW = 1 a longer decay time and larger hysteresis are
selected for input signals with strong video modulation (conventional intercarrier). This
bit has only an effect, If bit AGCOFF = 0. If bit AGCSLOW = 0 it selects normal attack
and decay times for the AGC and a small hysteresis.
1
AGCOFF
AGC on/off: if bit AGCOFF = 1 it forces the AGC block to a xed gain as dened in the
AGC gain register (see Section 7.3.2). If bit AGCOFF = 0 the AGC function is enabled
and the contents of the AGC gain register are ignored.
0
SIFSEL
SIF input select: if bit SIFSEL = 1 it selects pin SIF2 for input (recommended for satellite
tuner). If bit SIFSEL = 0 it selects pin SIF1 (recommended for terrestrial TV).
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