參數(shù)資料
型號(hào)： 93526374557
廠商： NXP SEMICONDUCTORS
元件分類： 接收器
英文描述： FM, AUDIO DEMODULATOR, PQFP44
封裝： PLASTIC, SOT-205, QFP-44
文件頁(yè)數(shù)： 44/71頁(yè)
文件大?。?/td> 269K
代理商： 93526374557
2000 Aug 04
49
Philips Semiconductors
Product specication
Digital TV sound demodulator/decoder
TDA9874A
7.4.7
TEST REGISTER 2 (TR2)
This register contains, as a binary number, the highest
subaddress used for slave receiver registers.
The first version will have the identification 0010 1101.
Table 86 Test register 2 (subaddress 252)
7.4.8
TEST REGISTER 1 (TR1)
This register contains, as a binary number, the highest
subaddress used for slave transmitter (status) registers.
The first version will have the identification 0000 0111.
Table 87 Test register 1 (subaddress 253)
7.4.9
DEVICE IDENTIFICATION CODE (DIC)
There will be several devices in the digital TV sound
processor family, with TDA9874A being the second
member. This byte is used to identify the individual family
members.
The first version will have the identification 0001 0001.
Table 88 Device identication code (subaddress 254)
7.4.10
SOFTWARE IDENTIFICATION CODE (SIC)
It is likely that during the life time of this family of devices
several versions of the DSP software will be made, e.g. to
incorporate new application concepts, respond to
customer wishes, etc. This byte is used to identify the
different releases.
The first version will have the identification 0000 0010.
Table 89 Software identication code (subaddress 255)
8I2S-BUS DESCRIPTION
The digital audio interface of the TDA9874A consists of a
serial audio output and associated clock signals. It can be
used to supply digital audio signals from received
TV programs to a suitable output device, e.g. a DAC or an
AES/EBU transmitter.
Two serial audio formats are supported at the digital audio
interface, the I2S-bus format and a very similar
MSB-aligned format. The difference is illustrated in Fig.8.
In both formats the left audio channel of a stereo sample
pair is output first, and is on the Serial Data line (SDO)
when the Word Select line (WS) is at LOW level. Data is
written on the trailing edge of SCK and read on the leading
edge of SCK. The most significant bit is sent first.
After Power-on reset, the outputs of the digital audio
interface are 3-stated to reduce EMC and allow for
combinations with other ICs. If an output is desired, it has
to be activated by means of an I2C-bus command.
When the output is enabled, serial audio data can be taken
from pin SDO. Depending on the signal source, switch and
matrix positions, the output can be either mono, stereo or
dual language.
The Word Select output (WS) is clocked with the audio
sample frequency of 32 kHz. The Serial Clock output
(SCK) is clocked at a frequency of 2.048 MHz. This means
that there are 64 clock pulses per pair of stereo output
samples, or 32 clock pulses per sample. There are
18 significant bits used on the Serial Data Output (SDO).
A symmetrical system clock output (SYSCLK) is available
from the TDA9874A as a master clock for external digital
audio devices. After Power-on reset, the clock is off. It can
be enabled and the output frequency set via an I2C-bus
command. Available output frequencies are 8.192, 12.288,
16.384 and 24.576 MHz.
76543210
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B1
B0
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76543210
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