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參數資料
| 型號： | 935265290112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 接收器 |
| 英文描述： | AM/FM, AUDIO DEMODULATOR, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁數： | 32/71頁 |
| 文件大?。?/td> | 304K |
| 代理商： | 935265290112 |
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2000 Aug 04
38
Philips Semiconductors
Product specication
Digital TV sound demodulator/decoder
TDA9874A
Table 57 System clock frequency select
SYSCL1
SYSCL0
SYSCLK OUTPUT
FREQUENCY
(MHz)
0
256fs
8.192
0
1
384fs
12.288
1
0
512fs
16.384
1
768fs
24.576
7.3.20
I2S-BUS OUTPUT SELECT REGISTER (I2SOSR)
This register is used to define both the signal source to be
output at the I2S-bus port and the mode of the digital matrix
for signal selection.
The two combinations of FM and NICAM shown in
Table 60 apply to the (rare) condition that three different
languages are being broadcast in an FM + NICAM system.
They allow for a two-out-of-three selection for special
applications. It should be noted that the controlling
microprocessor has to assure that the FM dematrix is set
to the mono position or bit IDSWFM is set to logic 1. If the
I2S-bus signal source is set to FM left or FM right it is
influenced by the automatic FM dematrix switching
(see subaddress 11).
The default setting after Power-on reset is 0000 0000.
Table 58 I2S-bus output select register (subaddress 22)
Table 59 Description of the I2S-bus output select register bits
Table 60 Mode of the digital matrix for signal selection (bit TVSMIIS = 0)
76543210
TVSMIIS
ICSM2
ICSM1
ICSM0
0
ISS1
ISS0
BIT
SYMBOL
DESCRIPTION
7
TVSMIIS
Auto-select function: for TV applications, only in combination with bit IDSWFM = 1. If
this bit is set to logic 1 it switches the matrix automatically, depending on the bits IDSTE
and IDDUA for FM and the bits S/MB, D/SB for NICAM in transmitters
subaddresses 0 and 1 (see Sections 7.4.1 and 7.4.2).
6
ICSM2
Output channel selection mode: these bits select the output channel selection mode;
see Table 60.
5
ICSM1
4
ICSM0
3
these bits are not used and should be set to logic 0
2
1
ISS1
Signal source: these bits select the signal source; see Table 60.
0
ISS0
ICSM2
ICSM1
ICSM0
L OUTPUT
R OUTPUT
REMARK
0
L input
R input
0
1
L input
0
1
0
R input
0
1
R input
L input
1
0
not allowed during use of high
deviation mode
L input
R input
+
2
-------------------------------------------
L input
R input
+
2
-------------------------------------------
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