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參數(shù)資料
| 型號： | 935266671518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 11/83頁 |
| 文件大小： | 316K |
| 代理商： | 935266671518 |
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Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Dec 01
16
12.5.3
Accessing the RDI register (Power–down, Power–up)
Accessing the RDI register is a special situation, but software written to access all other link base registers can still be used. This register can
be read and written with the link chip in power–down mode; this means that there is no system clock present within the link chip. The system
clock is required to access all other link registers due to the fact that multiple clock cycles are required to fetch data to the shadow register or
write data from the shadow register to the targeted internal register. Reading and writing to the RDI register is done through purely combinatoral
logic, there is no access through the shadow register. The RDI register is accessed directly through the host interface using the same method of
access required by other link base registers.
The RDI register contains control, status and interrupt bits. Operation of the status and interrupt bits in the RDI register differs slightly from these
types of bits in other registers. Operation falls into four categories: (1) pure status bit, (2) interrupt/status bit, (3) control bit, (4) interrupt control
bit.
LPSTAT is a pure status bit; this means that LPSTAT continually reflects the status of the LPS signal on the link–phy interface. If LPSTAT = 1,
the LPS signal is active. If LPSTAT = 0, the LPS signal to the phy chip is inactive. It should be noted here that the LPSTAT bit should NOT be
used as an indicator of link chip activity because the LPS signal may be inactive for short (25 uS) periods of time if the link chip is performing a
phy–link interface reset function. SCI is also a pure status bit when it is not enabled as an interrupt. SCI will reflect the INVERSE status of the
system clock at all times. When the system clock (SCLK) is active, SCI = 0. When the SCLK is inactive, SCI = 1. The SCI bit can also be used
as an interrupt bit by setting ESCI = 1. In this mode of operation when the SCI = 1, an interrupt will be generated to indicate that the SCLK has
become inactive. This interrupt is serviced in the same manner as all other link register interrupts... write a “1” back to the SCI bit position in
order to acknowledge the interrupt.
PLI, LOA and SCA are interrupt/status bits. These bits may be enabled as interrupts (by setting the corresponding interrupt control bit EPLI,
ELOA, or ESCA =1). These bits are ALSO status bits when the corresponding interrupt enabling bit is = 0. However, if any of these bits sets
(=1) while in the status bit mode, it must be written with a “1” to be reset... similar operation to interrupt bit operation elsewhere in the link
registers. Also, like other interrupt bits in the link registers, in order to acknowledge an interrupt of any of these bits, it is necessary to write a “1”
back to the bit position to acknowledge the interrupt; this resets the bit to “0”. [Please bear in mind that the functions represented by these bits
are continuous; so we recommend that before the interrupt is acknowledged, the corresponding enable bit should be set to “0”, else the interrupt
will immediately happen again.]
SWPD is a control bit. There are two ways to affect a power–down of the link chip. Setting SWPD will stop the link chip from transmitting the
LPS signal to the phy chip and thus cause the phy to withhold the SCLK, thus powering–down the link chip. Raising the link PD pin to the high
level will also accomplish power–down in a similar manner. DO NOT USE BOTH METHODS to affect a power–down. The SWPD bit, being a
control bit, will NOT reflect the state of the PD pin. If the SWPD bit is = 0 and the SCI bit is = 1, it’s a good bet that the PD pin is active if the phy
chip is operating. In this case the PD pin MUST be reset low before the link will power–up.
EPLI, ELOA, ESCA, and ESCI are interrupt enable bits. Setting any of these bits = 1 will cause the corresponding interrupt bit to become an
active interrupt when that bit sets. If these bits are set = 0, the corresponding PLI, LOA, SCA, and SCI bit is in the interrupt/status mode as
described above.
(Also see the individual bit descriptions in the RDI register section of this data sheet... Section 13.3.1)
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