- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24822 > 935266671518 (NXP SEMICONDUCTORS) 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | 935266671518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 14/83頁 |
| 文件大?。?/td> | 316K |
| 代理商： | 935266671518 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Dec 01
18
In Little Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 3. .0 from the left (most significant) to right (least significant)
as shown in Figure 5. To access a register in 8 bit HIF mode, at address N the CPU should use addresses E:
E = N + 3 ; to access the upper 8 bits of the register
E = N + 2 ; to access the upper middle 8 bits of the register
E = N + 1 ; to access the lower middle 8 bits of the register
E = N ; to access the lower 8 bits of the register
To access a register in 16 bit HIF mode, at internal address N, the CPU should used addresses E:
E = N ; to access the lower 16 bits of the register
E = N + 2 ; to access the upper 16 bits of the register
SV01079
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE 3
BYTE 2
BYTE 0
3130
BYTE 1
Figure 5.
Byte order in quadlets as implemented in the host interface, HIF LTLEND = HIGH
12.5.5
Accessing the asynchronous packet queues
Although entire incoming packets are stored in the receiver buffer memory they are not randomly accessible. These buffers act like FIFOs and
only the frontmost (oldest) data quadlet entry is accessible for reading. Therefore only one location (register address) is allocated to each of the
two receiver queues. Reading this location returns the head entry of the queue, and at the same time removes it from the queue, making the
next stored data quadlet accessible.
With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the shadow register. Once the data
is copied into the shadow register it is no longer available in the queue itself so the CPU should always read all 4 bytes, or both words, before
attempting any other read access (be careful with interrupt handlers for the PDI1394L41!).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 08-55-0134 | KK 156 TERMINAL CRIMP 18-24 AWG GOLD |
| 08-55-0133 | KK 156 TERMINAL CRIMP 18-24 AWG GOLD |
| 08-58-0111 | Connector |
| 08-50-0187 | Solderless Terminal; Body Material:Brass; Contact Plating:Tin; Series:6838; Wire Size (AWG):20-18; External Depth:0.11"; Lead Pitch:3.96"; Operating Temp. Min:0 C; Reel Quantity:7000; Voltage Rating:250V |
| 08-50-0189 | Solderless Terminal; Body Material:Brass; Contact Plating:Tin; Series:6838; Wire Size (AWG):20-18; External Depth:0.11"; Lead Pitch:3.96mm; Operating Temp. Min:0 C; Voltage Rating:250V RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
| 935269544557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。