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參數(shù)資料
| 型號： | 935266795557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 54/112頁 |
| 文件大?。?/td> | 693K |
| 代理商： | 935266795557 |
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1996 Jun 27
46
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xC592
13.5.12 TEST REGISTER (TR)
The Test Register is used for production testing only.
Table 53 Test Register (address 9)
13.5.13 TRANSMIT BUFFER LAYOUT
The global layout of the Transmit Buffer is shown in Fig.15. This buffer serves to store a message from the CPU to be
transmitted by the CAN-controller. It is subdivided into Descriptor and Data Field. The Transmit Buffer can be written to
and read from by the CPU.
13.5.13.1 Descriptor
Table 54 Descriptor Byte 1 Register (DSCR1, address 10)
Table 55 Descriptor Byte 2 Register (DSCR2, address 11)
Table 56 Description of the ID.n bits in DSCR1 and DSCR2
76543210
Reserved
Map Internal
Register
Connect RX
Buffer 0
CPU
Connect TX
Buffer CPU
Access
Internal Bus
Normal
RAM
Connect
Float Output
Driver
76543210
ID.10
ID.9
ID.8
ID.7
ID.6
ID.5
ID.4
ID.3
76543210
ID.2
ID.1
ID.0
RTR
DLC.3
DLC.2
DLC.1
DLC.0
BIT
SYMBOL
FUNCTION
DSCR1
7
ID.10
Identier. The Identier consists of 11 bits (ID.10 to ID.0). ID.10 is the most signicant
bit, which is transmitted rst on the bus during the arbitration process. The Identier acts
as the messages' name, used in a receiver for acceptance ltering, and also determines
the bus access priority during the arbitration process. The lower the binary value of the
Identier the higher the priority. This is due to the larger number of leading dominant bits
during arbitration (see Section 13.6.7).
6
ID.9
5
ID.8
4
ID.7
3
ID.6
2
ID.5
1
ID.4
0
ID.3
DSCR2
7
ID.2
Identier. See DSCR1.
6
ID.1
5
ID.0
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