參數(shù)資料
型號(hào): 935270030157
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù): 3/53頁(yè)
文件大?。?/td> 704K
代理商: 935270030157
Philips Semiconductors
SC16C650A
Universal Asynchronous Receiver/Transmitter (UART)
with 32-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 03 — 13 March 2003
11 of 49
9397 750 11207
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
a time-out function to ensure data is delivered to the external CPU. An interrupt is
generated whenever the Receive Holding Register (RHR) has not been read
following the loading of a character or the receive trigger level has not been reached.
6.3 Hardware ow control
When automatic hardware ow control is enabled, the SC16C650A monitors the CTS
pin for a remote buffer overow indication and controls the RTS pin for local buffer
overows. Automatic hardware ow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
ow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C650A will suspend TX transmissions as soon as the stop bit of the character in
process is shifted out. Transmission is resumed after the CTS input returns to a
logic 0, indicating more data may be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger level. However, under the above described conditions,
the SC16C650A will continue to accept data until the receive FIFO is full.
6.4 Software ow control
When software ow control is enabled, the SC16C650A compares one or two
sequential receive data characters with the programmed Xon or Xoff character
value(s). If received character(s) match the programmed Xoff values, the
SC16C650A will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) ags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C650A will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C650A will resume operation and
clear the ags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit ow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software ow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C650A compares two consecutive receive characters with two software ow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described ow control mechanisms, ow control
Table 4:
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS or
send Xoff
Assert RTS or
send Xon
8
16
0
16
24
7
24
28
15
28
23
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