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參數(shù)資料
| 型號： | 935272020125 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO5 |
| 封裝： | PLASTIC, SOT-353, 5 PIN |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 69K |
| 代理商： | 935272020125 |
2001 Apr 04
9
Philips Semiconductors
Product specication
Single D-type ip-op; positive-edge trigger
74LVC1G79
handbook, full pagewidth
MNA647
th
tsu
th
tPHL
tW
tPLH
tsu
1/fmax
VM
VI
GND
VI
GND
CP input
D input
VOH
VOL
Q output
Fig.6
Clock (CP) to output (Q) propagation delays, clock pulse width, D to CP set-up times, the CP to D hold
times and maximum clock pulse frequency.
VCC
VM
INPUT
VI
tr =tf
1.65 to 1.95 V
0.5
× VCC
VCC
≤ 2.0 ns
2.3 to 2.7 V
0.5
× V
CC
VCC
≤ 2.0 ns
2.7 V
1.5 V
2.7 V
≤ 2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
≤ 2.5 ns
4.5 to 5.5 V
0.5
× V
CC
VCC
≤ 2.5 ns
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage drop that occur with the output load.
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