參數(shù)資料
型號(hào)： 935285129112
廠商： NXP SEMICONDUCTORS
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LED DISPLAY DRIVER, PDSO28
封裝： 4.40 MM, PLASTIC, MO-153, SOT361-1, TSSOP-28
文件頁(yè)數(shù)： 33/54頁(yè)
文件大?。?/td> 410K
代理商： 935285129112
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PCA9685_2
NXP
B
.V
.2009.
All
r
ights
reser
v
ed.
Pr
oduct
data
sheet
Re
v
.02
—
16
J
u
ly
2009
39
of
50
NXP
Semiconductor
s
PCA9685
16-c
hannel,
12-bit
PWM
Fm+
I
2C-b
us
LED
contr
oller
13.
Dynamic
c
haracteristics
Table 14.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus
Fast-mode Plus
I2C-bus
Unit
Min
Max
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
0
1000
kHz
fEXTCLK
frequency on pin EXTCLK
DC
50
DC
50
DC
50
MHz
tBUF
bus free time between a STOP
and START condition
4.7
-
1.3
-
0.5
-
s
tHD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
s
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
0.26
-
s
tHD;DAT
data hold time
0
-
0
-
0
-
ns
tVD;ACK
data valid acknowledge time
0.3
3.45
0.1
0.9
0.05
0.45
s
tVD;DAT
data valid time
0.3
3.45
0.1
0.9
0.05
0.45
s
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
0.26
-
s
tf
fall time of both SDA and SCL
signals
-
300
20 + 0.1Cb[6]
300
-
120
ns
tr
rise time of both SDA and SCL
signals
-
1000
20 + 0.1Cb[6]
300
-
120
ns
tSP
pulse width of spikes that must
be suppressed by the input lter
-
50
-
50
-
50
ns
tPLZ
LOW to OFF-state propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-
40
-
40
-
40
ns
tPZL
OFF-state to LOW propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-
60
-
60
-
60
ns
tPHZ
HIGH to OFF-state propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-
60
-
60
-
60
ns
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