參數(shù)資料
型號(hào)： 93732AFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
封裝： 0.209 INCH, MO-150, SSOP-28
文件頁(yè)數(shù)： 6/11頁(yè)
文件大?。?/td> 126K
代理商： 93732AFT
4
ICS93732
0578I—05/18/05
Notes:
1.
Refers to transition on noninverting output.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
Timing Requirements
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Clock Frequency
freqop
Input Voltage level: 0-2.50V
22
340
MHz
Input Clock Duty Cycle
1
dtin
40
50
60
%
Clock Stabilization
1
tSTAB
from VDD = 2.5V to 1% target frequency
100
s
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
66 MHz
100
120
100 / 125/ 133/167MHz
48
65
200/267MHz
47
75
Phase Error
1
tpe
-150
150
ps
Output to output Skew
1
Tskew
20
100
ps
66 MHz to 100MHz
49.5
50
50.5
%
101MHz to 267 MHz
49
49.4
51
%
Rise Time, Fall Time
4
tR , tf
Load=120/14pF
579
950
ps
tc-c
Duty Cycle (Sign Ended)
1,3
DC
Cycle to cycle Jitter
1,2
相關(guān)PDF資料
PDF描述
93732AFLFT 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
93732AF 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
93732YFLFT 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
93735AF-T 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
93735AFLF 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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