參數(shù)資料
型號(hào)： 93732AFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
封裝： 0.209 INCH, MO-150, SSOP-28
文件頁(yè)數(shù)： 8/11頁(yè)
文件大?。?/td> 126K
代理商： 93732AFT
6
ICS93732
0578I—05/18/05
Bytes 0 to 4 are reseved power up default = 1. This allows operation with main clock.
Pin #
Name
0
1
PWD
Bit 7
2, 1
DDR0(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 6
4, 5
DDR1(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 5
-
Reserved
X
-
1
Bit 4
-
Reserved
X
-
1
Bit 3
13, 14
DDR2(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 2
17, 16
DDR3(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 1
-
Reserved
X
-
1
Bit 0
-
Reserved
X
-
1
Note:
Pin #
Name
0
1
PWD
Bit 7
-
Reserved
X
-
0
Bit 6
-
Reserved
X
-
0
Bit 5
-
Reserved
X
-
0
Bit 4
-
Reserved
X
-
1
Bit 3
24, 25
DDR4(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 2
-
Reserved
X
-
1
Bit 1
26, 27
DDR5(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 0
-
Reserved
X
-
1
Note:
Control Function
Affected Pin
BYTE
5
BYTE
6
PWD = Power Up Default
Type
Bit Control
Type
Control Function
Affected Pin
Bit Control
相關(guān)PDF資料
PDF描述
93732AFLFT 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
93732AF 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
93732YFLFT 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
93735AF-T 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
93735AFLF 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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