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參數(shù)資料
| 型號： | 93LC46A-SM |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | EEPROM |
| 英文描述： | 1K 2.5V Microwire Serial EEPROM |
| 中文描述： | 一千2.5V的微型導線串行EEPROM |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 222K |
| 代理商： | 93LC46A-SM |
93LC46/56/66
1997 Microchip Technology Inc.
DS11168L-page 3
2.0
PIN DESCRIPTION
2.1
Chip Select (CS)
A high level selects the device. A low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
CSL
) between
2.2
Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93LCXX.
Opcodes, addresses, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
CKL
). This gives the controlling master
freedom in preparing the opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1 to Table 2-6). CLK and DI then become don't
care inputs waiting for a new START condition to be
detected.
CKH
) and
2.3
Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4
Data Out (DO)
Data Out (DO) is used in the READ mode to output data
synchronously with the CLK input (T
tive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
CSL
) and an ERASE or WRITE operation has
been initiated.
The status signal is not available on DO, if CS is held
low or high during the entire WRITE or ERASE cycle. In
all other cases DO is in the HIGH-Z mode. If status is
checked after the ERASE/WRITE cycle, a pull-up
resistor on DO is required to read the READY signal.
PD
after the posi-
2.5
Organization (ORG)
When ORG is tied to V
tion is selected. When ORG is connected to Vcc or
floated, the (x16) memory organization is selected.
ORG can only be floated for clock speeds of 1 MHz or
less for the (X16) memory organization. For clock
speeds greater than 1 MHz, ORG must be tied to Vcc
or V
SS
.
SS
, the (x8) memory organiza-
Note:
CS must go low between consecutive
instructions.
相關PDF資料 |
PDF描述 |
|---|---|
| 93LC46A-SN | CAP, AL ELEC, AXIAL, 1000UF, 35V |
| 93LC46A-ST | 1K 2.5V Microwire Serial EEPROM |
| 93LC46A | 1K 2.5V Microwire Serial EEPROM |
| 93LC46B | 1K 2.5V Microwire Serial EEPROM |
| 93LC46B-IP | 1K 2.5V Microwire Serial EEPROM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 93LC46A-SN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K 2.5V Microwire Serial EEPROM |
| 93LC46A-ST | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K 2.5V Microwire Serial EEPROM |
| 93LC46AT-/SM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
| 93LC46AT/SN | 功能描述:電可擦除可編程只讀存儲器 128x8 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 93LC46AT-/SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
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