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參數(shù)資料
| 型號(hào)： | 950201YFLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 204K |
| 代理商： | 950201YFLF-T |
IDTTM Programmable Timing Control HubTM for P4TM
460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
11
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0)
Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3V66
3V66 pin to pin skew
0
500
ps
PCI
PCI_F and PCI pin to pin skew
0
500
ps
3V66 to PCI
S3V66-PCI
3V66 leads 33MHz PCI
1.5
3.5
ns
1Guaranteed by design, not 100% tested in production.
PD# Functionality
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相關(guān)PDF資料 |
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| 950201YGLF-T | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
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| 08053C103KA72A | General Specifications |
| 950211BFLFT | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
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