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參數(shù)資料
| 型號(hào)： | 950218AFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 331K |
| 代理商： | 950218AFLFT |
12
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950218
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%
PAR AMETER
SYMBOL
COND ITIONS
MIN
TYP
MAX
UN ITS
Input High Voltage
VIH
2VDD+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
m A
Input Low C urrent
IIL1
VIN = 0 V; Inputs with no pull-up res is tors
-5
m A
Input Low C urrent
IIL2
VIN = 0 V; Inputs with pull-up res is tors
-200
m A
Operating
C L = 0 pF; Select @ 66M
100
m A
Supply C urrent
C L = Full load
360
m A
IR EF=2.32
25
m A
IR EF= 5m A
45
m A
Input frequency
F
i
V
DD = 3.3 V;
14.318
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
C out
Out put pin capacitance
6
pF
CINX
X1 & X2 pins
27
36
45
pF
Trans ition Tim e
1
Ttrans
To 1s t cros s ing of target Freq.
3
m S
Settling Tim e
1
Ts
From 1s t cros s ing to 1% target Freq.
3
m S
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target Freq.
3
m S
tPZH,tPZH
output enable delay (all outputs )
1
10
nS
t
PLZ,tPZH
output dis able delay (all outputs )
1
10
nS
1Guarenteed by des ign, not 100% tes ted in production.
Input C apacitance
1
Delay
I
DD 3.3OP
Power Down
Supply C urrent
IDD3.3PD
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