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參數(shù)資料
| 型號(hào)： | 954201BGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56 |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大小： | 219K |
| 代理商： | 954201BGLF |
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12
Integrated
Circuit
Systems, Inc.
ICS954201
0819H—02/17/06
SMBus Table: SRC Stop Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRCCLK7
RW
Free-Running
Stoppable
0
Bit 6
SRCCLK6
RW
Free-Running
Stoppable
0
Bit 5
SRCCLK5
RW
Free-Running
Stoppable
0
Bit 4
SRCCLK4
RW
Free-Running
Stoppable
0
Bit 3
SRCCLK3
RW
Free-Running
Stoppable
0
Bit 2
SRCCLK2
RW
Free-Running
Stoppable
0
Bit 1
SRCCLK1
RW
Free-Running
Stoppable
0
Bit 0
SRCCLK0
RW
Free-Running
Stoppable
0
SMBus Table: Stop and Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
X
Bit 6
DOT_96MHz
Driven in PD
RW
Driven
Hi-Z
0
Bit 5
0
Bit 4
PCI_F1
RW
Free-Running
Stoppable
0
Bit 3
PCI_F0
RW
Free-Running
Stoppable
0
Bit 2
CPUCLK2_ITP
RW
Free-Running
Stoppable
1
Bit 1
CPUCLK1
RW
Free-Running
Stoppable
1
Bit 0
CPUCLK0
RW
Free-Running
Stoppable
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC_STOP Drive Mode
Driven in
PCI/SRC_STOP#
RW
Driven
Hi-Z
0
Bit 6
CPUCLK2_ITP_STOP Drive Mode
RW
Driven
Hi-Z
0
Bit 5
CPUCLK1_STOP Drive Mode
RW
Driven
Hi-Z
0
Bit 4
CPUCLK0_STOP Drive Mode
RW
Driven
Hi-Z
0
Bit 3
SRC_PD Drive Mode
RW
Driven
Hi-Z
0
Bit 2
CPUCLK2_ITP_PD Drive Mode
RW
Driven
Hi-Z
0
Bit 1
CPUCLK1_PD Drive Mode
RW
Driven
Hi-Z
0
Bit 0
CPUCLK0_PDDrive Mode
RW
Driven
Hi-Z
0
Driven in CPU_STOP#
Driven in Powerdown
(PD)
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
PCICLK_F outputs
RESERVED
Allow assertion of
CPU_STOP# to stop
CPUCLK outputs
RESERVED
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
SRC clocks
41,40
44,43
SRCCLK(7:0)
36,35
44,43
9
31,30
26,27
8
36,35
41,40
24,25
22,23
19,20
Byte 4
17,18
Byte 3
36,35
33,32
Byte 5
SRCCLK(7:0)
36,35
41,40
14,15
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PDF描述 |
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| 954201BF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 954201BGT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 954204BGLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 954204BGT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 954201BGLFT | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 954201BGLN | 制造商:Integrated Device Technology Inc 功能描述:PROGRAMMABLE PLL CLOCK SYNTHESIZER DUAL 56TSSOP - Rail/Tube |
| 954201BGLNT | 制造商:Integrated Device Technology Inc 功能描述:954201BGLNT - Tape and Reel |
| 954204BGLF | 制造商:Integrated Device Technology Inc 功能描述:56 TSSOP (LEAD FREE) - Rail/Tube |
| 954204BGLN | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin TSSOP Tube |
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