參數(shù)資料
型號(hào): 954204AGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
文件頁(yè)數(shù): 3/20頁(yè)
文件大?。?/td> 261K
代理商: 954204AGLFT
11
Integrated
Circuit
Systems, Inc.
ICS954204
0933D—03/16/05
SMBus Table: Output Enable Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
CPUCLK2_ITP/SRCCLK7
Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 6
1
Bit 5
SRCCLK5 Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 4
SRCCLK4/SATA Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 3
SRCCLK3 Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 2
SRCCLK2 Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 1
SRCCLK1 Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 0
SRCCLK0 Enable
Output Enable
RW
Disable (HiZ)
Enable
1
SMBus Table: PLL1 Spread and Output Enable Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
PCI_F0 Enable
Output Enable
RW
Disable
Enable
1
Bit 6
DOT_96MHz Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 5
USB_48MHz Enable
Output Enable
RW
Disable
Enable
1
Bit 4
REFOUT Enable
Output Enable
RW
Disable
Enable
1
Bit 3
-
Bit 2
CPU_1 Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 1
CPU_0 Enable
Output Enable
RW
Disable (HiZ)
Enable
1
Bit 0
Spread Spectrum Mode
(CPU, SRC, PCIF, PCI)
Spread Control for PLL1
RW
SPREAD OFF
SPREAD ON
0
SMBus Table: Output Enable Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
PCICLK5
Output Enable
RW
Disable
Enable
1
Bit 6
PCICLK4
Output Enable
RW
Disable
Enable
1
Bit 5
PCICLK3
Output Enable
RW
Disable
Enable
1
Bit 4
PCICLK2
Output Enable
RW
Disable
Enable
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
PCI_F1 Enable
Output Enable
RW
Disable
Enable
1
SMBus Table: SRC Free-Running Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
SRCCLK7
Free-Running Control
RW
Free-Running
Stoppable
0
Bit 6
0
Bit 5
SRCCLK5
RW
Free-Running
Stoppable
0
Bit 4
SRCCLK4/SATA
RW
Free-Running
Stoppable
0
Bit 3
SRCCLK3
RW
Free-Running
Stoppable
0
Bit 2
SRCCLK2
RW
Free-Running
Stoppable
0
Bit 1
SRCCLK1
RW
Free-Running
Stoppable
0
Bit 0
SRCCLK0
RW
Free-Running
Stoppable
0
Reserved
-
26, 27
19, 20
Free-Running Control, not
affected by PCI/SRC_STOP#
12
52
41, 40
-
17, 18
Byte 1
8
14,15
26, 27
24, 25
22, 23
19, 20
Byte 2
5
44, 43
-
Byte 0
35, 36
-
30, 31
4
3
56
17, 18
24, 25
22, 23
9
Byte 3
30, 31
35, 36
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