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參數(shù)資料
| 型號(hào)： | 954206BFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, M0-118N, SSOP-56 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 315K |
| 代理商： | 954206BFLFT |
12
Integrated
Circuit
Systems, Inc.
ICS954206B
Advance Information
0940—06/23/05
I
2C Table: Output Control Register
Control
Function
Bit 7
CPUCLK2_ITP/PCIEX6
Enable
Output Enable
RW
1
Bit 6
PCIEX5 Enable
Output Enable
RW
1
Bit 5
PCIEX4 Enable
Output Enable
RW
1
Bit 4
SATACLK Enable
Output Enable
RW
1
Bit 3
PCIEX3 Enable
Output Enable
RW
1
Bit 2
PCIEX2 Enable
Output Enable
RW
1
Bit 1
PCIEX1 Enable
Output Enable
RW
1
Bit 0
LCDCLK/PCIEX0 Enable
Output Enable
RW
1
I
2C Table: Spread and Output Control Register
Control
Function
Bit 7
Test Clock Mode Entry
Test Mode
RW
0
Bit 6
DOT_96MHz Enable
Output Enable
RW
1
Bit 5
USB_48MHz Enable
Output Enable
RW
1
Bit 4
REF_0 Enable
Output Enable
RW
1
Bit 3
LCDCLK/PCIEX0 Spectrum
Mode
Spread Control
RW
1
Bit 2
CPUCLK1
Output Enable
RW
1
Bit 1
CPUCLK0
Output Enable
RW
1
Bit 0
Spread Spectrum Mode
Spread Control for PLL1
RW
0
I
2C Table: Output Control Register
Control
Function
Bit 7
PCICLK5
Output Enable
RW
1
Bit 6
PCICLK4
Output Enable
RW
1
Bit 5
PCICLK3
Output Enable
RW
1
Bit 4
PCICLK2
Output Enable
RW
1
Bit 3
Test Mode Selection
RW
0
Bit 2
PCI_STOP
Stop all PCI, PCIEX and
SATA clocks
RW
1
Bit 1
PCI_F0 Enable
Output Enable
RW
1
Bit 0
PCI_F1 Enable
Output Enable
RW
1
I
2C Table: Output Control Register
Control
Function
Bit 7
PCIEX6
RW
0
Bit 6
PCIEX5
RW
0
Bit 5
PCIEX4
RW
0
Bit 4
SATACLK
RW
0
Bit 3
PCIEX3
RW
0
Bit 2
PCIEX2
RW
1
Bit 1
PCIEX1
RW
1
Bit 0
PCIEX0
RW
1
Disable
Enable
Disable
Enable
Disable
Enable
OFF
ON
-
Disable
Enable
Disable
Enable
Disable
Enable
Disable
-
Enable
Disable
Enable
-
Disable
Enable
OFF
Disable
ON
PWD
01
Byte 1
Pin #
Name
Type
-
Disable
Enable
01
Disable
Enable
PWD
-
Byte 0
Pin #
Name
Type
-
Disable
-
Free Running
-
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
PCIEX clocks
Free Running
Stoppable
Free Running
Stoppable
-
Enable
Stoppable
Disable
-
Enable
PWD
Stoppable
Enable
1
Enable
Stoppable
Disable
Stoppable
Enable
0
Disable
Byte 2
Pin #
Name
Type
-
0
Disable
Byte 3
Hi-Z
Pin #
Name
Type
Disable
-
Disable
Free Running
Stoppable
Free Running
Enable
1
REF/N
Free Running
Enable
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