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參數資料
| 型號： | 954206BFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, M0-118N, SSOP-56 |
| 文件頁數： | 6/20頁 |
| 文件大?。?/td> | 315K |
| 代理商： | 954206BFT |
14
Integrated
Circuit
Systems, Inc.
ICS954206B
Advance Information
0940—06/23/05
I
2C Table: Byte Count Register
Control
Function
Bit 7
BC7
RW
0
Bit 6
BC6
RW
0
Bit 5
BC5
RW
0
Bit 4
BC4
RW
0
Bit 3
BC3
RW
1
Bit 2
BC2
RW
1
Bit 1
BC1
RW
1
Bit 0
BC0
RW
1
I
2C Table: Watchdog Timer Register
Control
Function
Bit 7
WDH_EN
Watchdog Hard Alarm
Enable
RW
0
Bit 6
WDS_EN
Watchdog Soft Alarm
Enable
RW
0
Bit 5
WD Hard Status
WD Hard Alarm Status
R
X
Bit 4
WD Soft Status
WD Soft Alarm Status
R
X
Bit 3
WDTCtrl
Watch Dog Time base
Control
RW
0
Bit 2
WD2
WD Timer Bit 2
RW
1
Bit 1
WD1
WD Timer Bit 1
RW
1
Bit 0
WD0
WD Timer Bit 0
RW
1
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Bit 7
M/N_EN
PLLM/N Programming
Enable
RW
0
Bit 6
LCDCLK/PCIEX0 SEL
SELPCIEX0/LCDCLK#
RW
latch
Bit 5
REQ_SEL
RW
latch
Bit 4
LCDCLK/PCIEX0
Driven in PD
RW
0
Bit 3
WD Safe Freq Source
RW
0
Bit 2
WD SFC
RW
0
Bit 1
WD SFB
RW
0
Bit 0
WD SFA
RW
0
I
2C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div8
N Divider Prog bit 8
RW
X
Bit 6
N Div 9
N Divider Prog bit 9
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
Alarm
M Divider Programming
bits
LCDCLK
PCIEX0
-
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
1
0
-
PWD
Type
Name
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
PWD
-
PCIEX5
PEREQ
Byte 10
Pin #
Name
-
Normal
-
Latch
Inputs/Byte6[2:0]
These bits represent X*290ms (or 1.16S)
the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
290ms Base
B10b(2:0)
Name
Type
0
Disable
PWD
1
Byte 8
Name
Type
-
Byte Count Programming
b(7:0)
-
Byte 9
Pin #
-
Pin #
Byte 11
Pin #
0
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
Type
0
1
1160ms Base
Enable
Disable
Driven
Hi-Z
Disable
Enable
Alarm
Enable
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