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參數(shù)資料
| 型號(hào)： | 9701-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3000 MHz UltraCMOS⑩ Integer-N PLL Rad Hard for Space Applications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁(yè)數(shù)： | 11/13頁(yè) |
| 文件大小： | 280K |
| 代理商： | 9701-11 |
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Product Specification
PE9701
Page 7 of 13
Document No. 70-0035-02
│ www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Functional Description
The PE9701 consists of a prescaler, counters, a
phase detector, a charge pump, and control logic.
The dual modulus prescaler divides the VCO
frequency by either 10 or 11, depending on the
value of the modulus select. Counters “R” and
“M” divide the reference and prescaler output,
respectively, by integer values stored in a 20-bit
register. An additional counter (“A”) is used in the
modulus select logic. The phase-frequency
detector generates up and down frequency control
signals. The control logic includes a selectable
chip interface. Data can be written via serial bus,
parallel bus, or hardwired directly to the pins.
There are also various operational and test modes
and a lock detect output.
Figure 4. Functional Block Diagram
Control
Logic
Modulus
Select
10/11
Prescaler
M Counter
(9-bit)
R Counter
(6-bit)
Phase
Detector
2 k
fc
PD_U
PD_D
LD
Cext
fp
R(5:0)
M(8:0)
A(3:0)
D(7:0)
Sdata
Control
Pins
fr
Fin
Charge
Pump
CP
Fin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9702-01 | 3.0 GHz Integer-N PLL for Rad Hard Applications |
| 9702-11 | 3.0 GHz Integer-N PLL for Rad Hard Applications |
| 9704-01 | 3.0 GHz Integer-N PLL for Rad Hard Apllications |
| 9704-11 | 3.0 GHz Integer-N PLL for Rad Hard Apllications |
| 971-36006-21 | 36 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, PRESS FIT |
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