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| 型號： | 9701-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3000 MHz UltraCMOS⑩ Integer-N PLL Rad Hard for Space Applications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 280K |
| 代理商： | 9701-11 |
Product Specification
PE9701
Page 4 of 13
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0035-02
│ UltraCMOS RFIC Solutions
Table 1. Pin Descriptions (continued)
Note 1:
VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
VDD pins 31 and 38 are used to enable test modes and should be left floating.
Note 2:
All digital input pins have 70 k
pull-down resistors to ground.
Pin No.
Pin Name
Interface Mode
Type
Description
31
VDD-fp
ALL
(Note 1)
VDD for fp
32
Dout
Serial, Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
33
VDD
ALL
(Note 1)
Same as pin 1.
34
Cext
ALL
Output
Logical “OR” of PD_U and PD_D terminated through an on chip, 2 k
series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
35
VDD
ALL
(Note 1)
Same as pin 1.
36
CP
ALL
Output
Charge pump current is sourced for “up” when fc leads fp and sinked for “down”
when fc lags fp.
37
NC
ALL
No connection.
38
VDD-fc
ALL
(Note 1)
VDD for fc
39
fc
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
40
GND
ALL
Ground.
41
GND
ALL
Ground.
42
fr
ALL
Input
Reference frequency input.
43
LD
ALL
Output,
OD
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
44
Enh
Serial, Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
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