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參數(shù)資料
| 型號： | 9702-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3.0 GHz Integer-N PLL for Rad Hard Applications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 262K |
| 代理商： | 9702-11 |
Product Specification
PE9702
Page 7 of 13
Document No. 70-0036-02
│ www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Functional Description
The PE9702 consists of a prescaler, counters, a
phase detector, and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired directly to the pins.
There are also various operational and test modes
and a lock detect output.
Figure 4. Functional Block Diagram
Control
Logic
R Counter
(6-bit)
Phase
Detector
fc
PD_U
PD_D
LD
R(5:0)
M(8:0)
A(3:0)
D(7:0)
Sdata
Control
Pins
fr
Modulus
Select
10/11
Prescaler
M Counter
(9-bit)
Cext
fp
Fin
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