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參數(shù)資料
| 型號： | 9702-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3.0 GHz Integer-N PLL for Rad Hard Applications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 262K |
| 代理商： | 9702-11 |
Product Specification
PE9702
Page 10 of 13
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0036-02
│ UltraCMOS RFIC Solutions
Figure 6. Serial Interface Mode Timing Diagram
Figure 5. Parallel Interface Mode Timing Diagram
t
DHLD
t
DSU
t
PW
t
CWR
t
WRC
t
PW
D
M1_WR
M2_WR
A_WR
E_WR
Hop_WR
[]
0
:
7
t
DHLD
t
DSU
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
t
EC
t
CE
E_WR
Sdata
Sclk
S_WR
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| 9704-01 | 3.0 GHz Integer-N PLL for Rad Hard Apllications |
| 9704-11 | 3.0 GHz Integer-N PLL for Rad Hard Apllications |
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| 97021604 | 制造商:Laird Technologies Inc 功能描述:CSTR FRG AG |
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