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參數(shù)資料
| 型號： | 9704-01 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3.0 GHz Integer-N PLL for Rad Hard Apllications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 247K |
| 代理商： | 9704-01 |
Product Specification
PE9704
Page 7 of 10
Document No. 70-0083-03
│ www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Register Programming
Serial Interface Mode
Serial Interface Mode is selected by setting the
DMODE input “l(fā)ow”.
While the E_WR input is “l(fā)ow”, serial data (DATA
input), B0 to B19, is clocked into a buffer register on
the rising edge of CLOCK, LSB (B0) first. The
contents from this buffer register are transferred
into the frequency control register on the rising
edge of S_WR according to the timing diagram
shown in Figure 4. This data controls the
counters as shown in Table 7.
While the E_WR input is “high”, serial data (DATA
input), B0 to B7, is clocked into a buffer register on
the rising edge of CLOCK, LSB (B0) first. The
contents from this buffer register are transferred
into the enhancement register on the falling edge
of E_WR according to the timing diagram shown
in Figure 4. After the falling edge of E_WR, the
data provides control bits as shown in Table 8.
These bits are active when the
Enh input is “l(fā)ow”.
Direct Interface Mode
Direct Interface Mode is selected by setting
the DMODE input “high”. In this mode, the counter
values are set directly at external pins as shown in
Table 7 and Figure 2. All frequency control
register bits are addressable except PB (it is not
possible to bypass the ÷10/11 dual modulus
prescaler in Direct Mode).
MSB (first in)
(last in) LSB
Table 7.
Frequency Register Programming
Table 8. Enhancement Register Programming
* Data is clocked serially on CLOCK rising edge while E_WR is “l(fā)ow” and transferred to frequency register on S_WR rising edge.
* Program to 0
* Data is clocked serially on CLOCK rising edge while E_WR is “l(fā)ow” and transferred to frequency register on S_WR rising edge.
MSB (first in)
(last in) LSB
Interface
Mode
Enh
DMODE
R5
R4
M8
M7
X
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Serial*
1
0
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
Direct
1
R5
R4
M8
M7
0
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Interface
Mode
Enh
DMODE
Reserved*
fp output
Power
down
Counter
load
MSEL
output
fc output
PB
Serial**
0
X
B0
B1
B2
B3
B4
B5
B6
B7
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