參數(shù)資料
型號(hào)： 97CFDC
廠(chǎng)商： SMSC Corporation
英文描述： USB FLOPPY DISK CONTROLLER
中文描述： 軟盤(pán)控制器的USB
文件頁(yè)數(shù)： 20/20頁(yè)
文件大?。?/td> 143K
代理商： 97CFDC
SMSC DS – USB97CFDC
Page 9
Rev. 12/15/2000
PIN NO.
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
MISCELLANEOUS
17
Crystal
Input/External
Clock Input
XTAL1/
CLKIN
ICLKx
14.318Mhz Crystal or clock input.
This pin can be connected to one terminal of the
crystal or can be connected to an external
14.318Mhz clock when a crystal is not used.
18
Crystal
Output
XTAL2
OCLKx
14.318Mhz Crystal
This is the other terminal of the crystal, or left
open when an external clock source is used to
drive XTAL1/CLKIN. It may not be used to drive
any external circuitry other than the crystal circuit.
23
SRAM Enable nMEMEN
O24
An active low signal is output on this pin to enable
the optional external SRAM for extended FDC
write and read caching for ultra high performance
applications.
24
Option Enable OPTEN
I
Current
firmware
utilizes
this
input
pin
for
detecting the media density switch of the drive.
Various firmware options are available for different
polarities of this signal.
Contact
factory
for
available firmware options. If this pin is not driven
by the drive, it should be tied low.
25
Drive Ready
nDRVRDY
I
An active low signal on this pin from the floppy
disk drive, after DS0 goes active, indicates that
the system may activate MTR0. If the drive does
not supply this signal, this pin should be tied low.
26
Drive Power
nFDPWR
OD24
This active low signal is intended to activate an
external power switch, either in the drive or on the
system board, to supply power to the floppy disk
drive. It is active whenever the USB97CFDC is not
in SUSPEND mode.
21
RESET input
nRESET
IS
This active low signal is used by the system to
reset the chip. The active low pulse should be at
least 100ns wide.
22
Test output
TSTOUT
O8
This signal is used for testing the chip via an
internal XNOR chain. User should normally leave
it unconnected.
15
Test input
nTEST
I
This signal is a manufacturing test pin. It should
be tied to VDD for normal operation.
16
Test Enable
nTESTEN
I
This active low signal places the device into board
test mode using the XNOR chain. For normal
operation this pin should be tied high. See Board
Test Mode Operation on page 10
POWER, GROUND, AND NO CONNECTS
14, 39, 60,
82, 93
VDD
+3.3V power
8, 19, 27, 43,
52, 66, 79,
81, 88
GND
Ground Reference
20, 51, 78,
80, 83, 94-96
NC
No Connect. These pins should not be connected
externally.
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