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參數(shù)資料
| 型號： | 97CFDC |
| 廠商： | SMSC Corporation |
| 英文描述： | USB FLOPPY DISK CONTROLLER |
| 中文描述： | 軟盤控制器的USB |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 143K |
| 代理商： | 97CFDC |
SMSC DS – USB97CFDC
Page 17
Rev. 12/15/2000
Table 2 - Full Speed (12Mbps) Source Electrical Characteristics
PARAMETER
SYM
CONDITIONS
(NOTE 1, 2, 3)
MIN
TYP
MAX
UNIT
Driver Characteristics
Transition Time:
Rise Time
Fall Time
TR
TF
Note 4,5 and
FIGURE 7
CL = 50 pF
4
20
ns
Rise/Fall Time Matching
TRFM
(TR/TF)
90
110
%
Output Signal
Crossover Voltage
VCRS
1.3
2.0
V
Drive Output
Resistance
ZDRV
Steady State Drive
28
43
Data Source Timing
Full Speed Data Rate
TDRATE
Ave. Bit Rate
(12 Mb/s +/-
0.25%) Note 8
11.95
12.03
Mbs
Frame Interval
TFRAME
1.0 ms +/- 0.05%
0.999
5
1.0005
ms
Source Differential
Driver Jitter
To next Transition
For Paired Transitions
TDJ1
TDJ2
Note 6, 7 and
FIGURE 8
-3.5
-4.0
3.5
4.0
ns
Source EOP Width
TEOPT
Note 7 and
FIGURE 9
Differential to EOP
transition Skew
TDEOP
Receiver Data Jitter
Tolerance
To next Transition
For Paired Transitions
TJR1
TJR2
Note 7 and
-18.5
-9
18.5
9.0
ns
EOP Width at receiver
Must reject as EOP
Must Accept
TEOPR1
TEOPR2
Note 7 and
FIGURE 9
40
82
ns
Cable Impedance and Timing
Cable Impedance (Full
Speed)
ZO
(45
+/- 15%)
38.75
51.75
Cable Delay (One Way)
TCBL
30
ns
Note 1: All voltages are measured from the local ground potential, unless otherwise specified.
Note 2: All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified.
Note 3: Full speed timings have a 1.5K
pull-up to 2.8 V on the D+ data line.
Note 4: Measured from 10% to 90% of the data signals.
Note 5: The rising and falling edges should be smoothly transiting (monotonic).
Note 6: Timing differences between the differential data signals.
Note 7: Measured at crossover point of differential data signals.
Note 8: These are relative to the 14.318 MHz crystal.
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