參數(shù)資料
型號: 992215732001
廠商: NXP SEMICONDUCTORS
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, CDIP32
封裝: CERAMIC, DIP-32
文件頁數(shù): 13/16頁
文件大小: 234K
代理商: 992215732001
2000 January
6
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FT 18
Timing diagrams (for default operation)
Figure 3 - Line and pixel timing diagrams
H
L
SSC
H
L
H
L
H
L
C1
C2
C3
Tp/6 = (1/36MHz)/6 = 4.63ns
dummy
1
..
.
dummy
7
black
1
..
.
black
20
timing
1
timing
4
pixel
1
..
.
pixel
1024
timing
1
timing
4
black
1
..
.
black
20
dummy
1
H
L
RG
Tp = 1/36MHz = 27.8ns
..
.
..
.
In this figure, charge is transported to the left output buffer (normal readout) by moving it from C1 to C2 to C3 etc.
By exchanging the timing of C1 and C2, charge will be transported to the right output buffer (mirrored readout).
A1
A2
A3
A4
Phase
or
pixel count
1100 1110 1120 1130 1140
10
20
30
40
50
60
70
80
90
100
110
120
L
H
L
H
L
H
L
H
B2
B3
B4
B1
L
H
L
H
L
H
L
H
19
64
28
37
46
55
32
62
26
44
38
56
20
50
SSC
L
H
72
1150
0
One cycle of the storage gates (during line blanking), moving one line from storage to output register
C clocks stopped for 2 microseconds
L
H
PB
0
L
H
BLC
0
79
L
H
CB
1131
99
1080 pixels until 1152
1/(36MHz) = 27.8ns
One charge pumping cycle of the image gates (during line blanking), shifting the charge of one line back and forth
Start-Stop C-clocks
Pre-Blanking
Black Level Clamp
Composite Blanking
L
CR
19
64
Charge Reset
H
1.25 microseconds
AC Characteristics
Min.
Typical
Max.
Unit
Horizontal frequency (1/Tp)
Vertical frequency
-
36
750
40
833
MHz
kHz
Line Timing
Pixel Timing
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