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參數(shù)資料
| 型號： | 9DB106BFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 152K |
| 代理商： | 9DB106BFLFT |
IDT
Six Output Differential Buffer for PCIe Gen 2
9DB106
REV K 04/20/11
9DB106
Six Output Differential Buffer for PCIe Gen 2
6
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Outputs
TA = TCOM or TIND; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, IREF = 475
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Current Source Output
Impedance
Zo
1
VO = Vx
3000
<
1
Voltage High
VHigh
660
850
1,3
Voltage Low
VLow
-150
150
1,3
Max VoltageVovs
1150
1,3
Min VoltageVuds
-300
1,3
Crossing Voltage (abs)
Vcross(abs)
250
550
mV
1,3
Crossing Voltage (var)
d-Vcross
Variation of crossing over all edges
140
mV
1,3
Long Accuracy
ppm
see Tperiod min-max values
0
ppm
1,2
100.00MHz nominal
9.9970
10.0030
ns
2
100.00MHz spread
9.9970
10.0533
ns
2
Absolute min period
Tabsmin
100.00MHz nominal/spread
9.8720
ns
1,2
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
125
ps
1
Fall Time Variation
d-tf
125
ps
1
tpd
PLL Mode.
0
150
ps
1
tpdbyp
Bypass mode
3.7
4.2
ns
1
Duty Cycle
dt3
Measurement from differential
wavefrom
45
55
%
1
Output-to-Output Skew
tsk3
VT = 50%
40
50
ps
1
PLL mode,
Measurement from differential
wavefrom
35
50
ps
1
BYPASS mode as additive jitter
35
50
ps
1
1Guaranteed by design and characterization, not 100% tested in production.
3I
REF = VDD/(3xRR).
For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
2 The 9DB106 does not add a ppm error to the input clock.
Jitter, Cycle to cycle
tjcyc-cyc
Average period
Tperiod
Input to Output Delay
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value.
mV
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| 9DB106BFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB106BGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
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| 9DB106BGILF | 功能描述:時鐘緩沖器 6 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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| 9DB106BGLF | 功能描述:時鐘緩沖器 6 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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