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參數(shù)資料
| 型號(hào)： | 9DB106BFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 152K |
| 代理商： | 9DB106BFLFT |
IDT
Six Output Differential Buffer for PCIe Gen 2
9DB106
REV K 04/20/11
9DB106
Six Output Differential Buffer for PCIe Gen 2
3
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
PLL_BW
IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
2
CLK_INT
IN
True Input for differential reference clock.
3
CLK_INC
IN
Complementary Input for differential reference clock.
4
vCLKREQ1#
IN
Output enable for PCI Express output pair 1.
0 = enabled, 1 =disabled
5
PCIEXT0
OUT
True clock of differential PCI_Express pair.
6
PCIEXC0
OUT
Complementary clock of differential PCI_Express pair.
7
VDD
PWR
Power supply, nominal 3.3V
8
GND
IN
Ground pin.
9
PCIEXT1
OUT
True clock of differential PCI_Express pair.
10
PCIEXC1
OUT
Complementary clock of differential PCI_Express pair.
11
PCIEXT2
OUT
True clock of differential PCI_Express pair.
12
PCIEXC2
OUT
Complementary clock of differential PCI_Express pair.
13
VDD
PWR
Power supply, nominal 3.3V
14
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
15
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
16
VDD
PWR
Power supply, nominal 3.3V
17
PCIEXC3
OUT
Complementary clock of differential PCI_Express pair.
18
PCIEXT3
OUT
True clock of differential PCI_Express pair.
19
PCIEXC4
OUT
Complementary clock of differential PCI_Express pair.
20
PCIEXT4
OUT
True clock of differential PCI_Express pair.
21
GND
PWR
Ground pin.
22
VDD
PWR
Power supply, nominal 3.3V
23
PCIEXC5
OUT
Complementary clock of differential PCI_Express pair.
24
PCIEXT5
OUT
True clock of differential PCI_Express pair.
25
vCLKREQ4#
IN
Output enable for PCI Express output pair 4.
0 = enabled, 1 =disabled
26
IREF
OUT
This pin establishes the reference for the differential current-mode
output pairs. It requires a fixed precision resistor to ground.
475ohm is the standard value for 100ohm differential impedance.
Other impedances require different values. See data sheet.
27
GNDA
PWR
Ground pin for the PLL core.
28
VDDA
PWR
3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
相關(guān)PDF資料 |
PDF描述 |
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| 9DB106BFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB106BGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB106BGILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB106BGILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB106BFILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB106BGILF | 功能描述:時(shí)鐘緩沖器 6 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB106BGILFT | 功能描述:時(shí)鐘緩沖器 6 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB106BGLF | 功能描述:時(shí)鐘緩沖器 6 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB106BGLFT | 功能描述:時(shí)鐘緩沖器 6 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB106CFLF | 制造商:Integrated Device Technology Inc 功能描述:9DB106CFLF - Rail/Tube |
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